JPS61160129A - Timing generating circuit - Google Patents

Abstract

PURPOSE:To make a timing generating circuit suitable for high integration and temporally setting up a timing output by providing the circuit with plural gate groups for cascade connection and selecting any one input from the plural gate groups or an output on the basis of a program. CONSTITUTION:One bit in a circulating shift register 31 is turned to '1' by using a starting signal and a clock signal CLK. At that time, only a memory cell string connected to a corresponding word line is selected and other word lines are kept at non-selected state. A timing pattern signal and selecting information are inputted to writing data terminals 34-37 and a signal specifying writing operation (actually a binary signal '0' or '1') is inputted to a reading/ writing operation control terminal 33. On the other hand, the reading operation is executed by detecting the potential values of respective bit lines of a selected F/F type memory cell array by reading circuits 10-13 and reading out respective information in the F/F type memory cell array by circuits 10-13 and respective information in the F/F type memory cell array is read out. At that time, the terminal 33 is reading operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable timing generation circuit used in an information processing device requiring multiphase timing signals.

(Prior Art) Generally, an information processing device requires a plurality of timing circuits, and conventionally, a timing generation circuit has been configured with a plurality of cascade-connected nine gate groups. In such a configuration according to the prior art, one of the input terminals and output terminals of the gate group is connected to the input terminal of the other gate group by a conductive wire of printed wiring to form a cascade connection.

(Problems to be Solved by the Invention) In the programmable timing generation circuit according to the prior art, the number of gate stages is changed to generate various delays with respect to the input of the timing signal input from the input terminal of the first stage. Since a timing output signal having time is obtained, it is difficult to change the setting of the timing output signal, lacks versatility, and requires a large number of external terminals.

An object of the present invention is to provide a plurality of gate groups for a plurality of cascade connections, and to select one of the input or output of the plurality of gate groups for cascade connections by a program. It is an object of the present invention to provide a programmable timing generation circuit that eliminates the drawbacks, is suitable for high integration, and is configured so that timing output can be temporarily set.

(Means for Solving the Problems) A timing generation circuit according to the present invention includes a plurality of cascaded gate groups, a plurality of selection circuits, a circular shift register, a plurality of memory cells, a write circuit, and a plurality of cascaded gate groups. This configuration includes a readout circuit.

The plurality of selection circuits are provided in the column direction corresponding to the plurality of cascaded gate groups in order to select one of the inputs and outputs of the plurality of cascaded gate groups.

The circular shift register is provided in the row direction, and is used to receive an activation signal, shift the register in response to a clock, and send out an output for each bit.

A plurality of memory cells are selected by a circular shift register and are arranged in a matrix to store selection signals and timing patterns for controlling a plurality of selection circuits.

The write circuit is for writing selection signals and timing patterns into a plurality of memory cells.

The plurality of readout circuits are provided corresponding to the plurality of selection circuits in order to read selection signals and timing patterns from the plurality of memory cells.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram 69 showing one embodiment of a timing generation circuit according to the present invention, and FIG. 2 is a circuit diagram of a flip-flop (F/F) type memory cell shown in FIG. 1.
FIG. 8 is a waveform chart showing waveforms of the input/output terminals for explaining the operation of the embodiment shown in FIG. 1 of the present invention.

In FIG. 1, selection circuits 1, 6.9 for outputting input or output for each of the delay gate groups 24 to 26 and the delay gate groups 24 to 2B by selection signals on signal lines 27 to 29, respectively. and 7 flip-flop (F/F) type memory cells 151 to 154 for writing selection signals and timing pattern signals.
161-164.171-174.181-184,
F/F type meko memory cells 151-15461-184.
Readout circuits 10 to 10 for reading selection signals and timing pattern signals from 171 to 174 and 181 to 184;
13, the selection signal and the timing pattern signal to F/
F type meko memory cell 1B1154, 161 to 184, 1
71 to 174, a write circuit 25 for writing to 181 to 184, and F/F type meko memory cells 151 to 15461
164, 171-174, and 181-184 as memory cell columns each time. Here, the delay gate group 24 consists of delay gates 2 to 6, the delay gate group 25 consists of delay gates 7 and 8, and the delay gate 26 consists of one delay gate 26. 500~IO
s are each current sources.

F/F type meko memory cells 161-15461-164.
171 to 174, 181 to 184 all have the same configuration, and are F/F type mesememory cell loss-coupled multi-emitter transistors 1G1, 1 (1,
and resistor 1GiS.

104 forms a flip-flop.

One emitter of transistors 101.10ffi is connected to read circuits 10-15 and write circuit 2s through bit lines DitDi (1=o, 1t2+8), respectively. The other emitter is connected to a current source s00-80s for holding the contents of the memory cells.

Each F/F type mesememory cell line Wj (j=1.2,8
．． 4) is selected and a read operation or a write operation is performed. These F/F type mesememory cells 151-15461-164゜171-1
74, 181-184 operate as a type of read/write memory for storing binary information.

Next, referring to FIG. 8, the clock signal CLK is set as shown in FIG.
) as shown in FIG.
The operation of applying a start signal as shown in FIG. 8(b) to 2 to obtain a timing pattern signal as shown in FIG. 8(C) will be explained.

In addition, F/F type meko memory cells 151 to 16461 to 1
The writing circuit 25 writes selection signal information and timing pattern signals to 64, 171 to 174, 181 to 184. Tamashii, start signal and clock signal C
Using LK'G, one bit in the circular shift register 51 is set to %11. At this time, only the memory cell column connected to the corresponding word line is selected, and the other word lines are kept unselected. Write data terminals 54-57
(DO to D8), input the timing pattern signal and selection signal information to the read/write operation control terminal δδ(E
NABLE ) write operation (actually %Ql and 1
This is done by specifying 11 binary values). That is, based on the information given to the write data terminals 84 to 57, the write circuit 23 sets the potential of the bit line to a high level or a low level, so that the F/F
Type Mesemememory Cell 151-15461-184.171
~174. Set the flip-flops from 181 to 184.

By shifting the output of the circular shift register 31 as described above, each F/F type mesememory cell 151 to 15
Columns 461-164, 171-174, and 181-184 are selected and written.

On the other hand, in the read operation, the potential of each bit line of the selected F/F type memory cell column is detected by the readout circuits 10 to 1s, and the information of each F/F type female memory cell column is read out. . At this time, the terminal 35 serves as a read operation button.

Here, the F/F type mesememory cell 1 is
Story 11 is written in 525, 5, 162, 164, 174, and other F/F type mesoricells 151, 154, 161.
It is assumed that %Ol is written in 183, 171-173 degrees and 181-184. The state on the terminal 38 is set to read operation, and at timing t0, the input activation signal changes from low level to high level, and at timing t1, the first bit SOK of the circular shift register 31 is set to p% by the clock signal. 11 is set. As a result, the word lines W2, W8, and W4 are at a high level, and the word line W1 is selected and becomes a low level. The F/F type memory cells 151-164 are selected and information is read out. At this time, since each F/F type mesememory cell 101 is being written, the final output terminal! The state of 8 becomes 101. Here, it is assumed that the selection signal is %11 and an output is obtained when the output of each gate group is .beta.Ol.

Next, at timing t, %11 is set in the 81st bit of the circular shift register s1 by the clock signal, the word line W2 is selected, and the F/F type mesememory cell 152 is selected.
Information of 62, 172, and 182 is read out. At this time,
Since 111 has been written in the F/F type memory cell IS2, the state of the output terminal S8 will eventually become %11.

However, the F/F type memory cell 16 read out at the same time
The information for 272.111 is %l I and %Q I, respectively.
.

%Ol, this information serves as a selection signal for the selection circuits 9 and 6.1.The rounded F/F type mesememory cell 152 information passes through the delay gate 26 and is output from the output terminal 58.

Next, 1 timing 1. Now, 8 of the circular shift register 31
2 bits are set to %11, and word line W8 is selected. In this case, the F/F type meko memory cell 15
Information of 1$6i$, 175,185 is read. However, since the F/F type mesememory cell 163%II has been written, there is no change in the output terminal 58, and the F/F type mesememory cell 16i$7! , 18! It has nothing to do with the content.

Next, at timing t4, the 88 bits of the circular shift register 51 are set to %I, Ji, and the word line W
4 is selected. In this case, the information of the F/F type mekomemory cells 14, 164, 174, and 184 is read out. At this time, F/F type meko memory cell 154%O
Since 1 has been written, the state on the output terminal 38 will eventually become %OI. However, F/F read at the same time
The information of the memory cells 16474 and 184 are % l # and % l #, respectively.

%Ol, and this information is the selection circuit! Since it is a selection signal for the selection circuit 1, 8.1, the F/F type meko memory cell 154 signal passes through the gate group 2B and the gate group 25 and is output from the output terminal i$8. i.e. 8-stage delay game)? , 8.28, the delayed timing output is obtained. Circular shift register by gate 14! Since the SO bit of 1 and the S8 bit are connected, the state at timing t4 is the same as at timing t1, and a repeated operation is performed.

As described above, the F/F type meko memory cells 161 to 15 are
4 KF/F type memosa memory cells for storing timing pattern information~164, 171~174, 181~1
At 84, time delay information is stored to obtain an arbitrary timing signal. In the above, it can be easily inferred that by increasing the number of F/F memory cells for timing pattern information, a more complex timing signal can be obtained.

(Effects of the Invention) As described above, in the present invention, the rising timing and falling timing of the clock signal KFI, any timing pattern signal, and start signal can be independently set by a program, thereby providing versatility in the circuit. Since the number of external terminals can be reduced, it is suitable for high integration and can be programmed.

In the embodiment of the present invention, a cyclic shift register is used to perform the cyclic operation, but a counter may also be used. In addition, the memory cell is a 7-lip-flop type (F
/F' type) memory cells are used, but it goes without saying that applications using memory cells such as FROM can also be considered.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a timing generation circuit according to the present invention. FIG. 2 is a circuit diagram showing the FIF type metronome memory cell structure shown in FIG. 1. FIG. 8 is a waveform diagram illustrating the operation of the timing generation circuit shown in FIG. 1. 1.6.9...-Selection circuit 2-B, 7, 8, 14, 26... Gate 10-15.
・Threatening circuit 151-164, 161-164, 171-174゜1
81~184・φ−・@F/F type memosa memory cell 23
...Write circuit 51...Circular shift register 1G1, 102...Transistor 103.104...Resistor, 500-503...Current source 30.32-38...Terminal 21-29.・Φ signal line diagram 2

Claims (1)

[Claims] In order to select one of the plurality of cascaded gate groups and the input and output of the plurality of cascaded gate groups, a plurality of cascaded gate groups are provided in the column direction corresponding to the plurality of cascaded gate groups. Input the selection circuit and start signal,
a circular shift register provided in the row direction for shifting in response to a lock and sending out an output for each bit; and a selection signal selected by the circular shift register for controlling the plurality of selection circuits. a plurality of memory cells arranged in a matrix for storing timing patterns; a write circuit for writing the selection signal and the timing pattern into the plurality of memory cells; and a write circuit for writing the selection signal and the timing pattern into the plurality of memory cells; A timing generation circuit comprising: a plurality of readout circuits provided corresponding to the plurality of selection circuits for reading from the plurality of memory cells.