JPS63113896A - Non-volatile semiconductor device - Google Patents

Abstract

PURPOSE:To time-division-process the sense of respective bits of a designated address based on a timing with one sense circuit and to decrease the number of circuits by generating a time division timing at the time of reading and latching input data to a shift register at the time of writing. CONSTITUTION:When a non-volatile semiconductor device is programed, a signal 67 is made into H and input data 10-13 are inputted to D type F/F34-37. At the time of reading, setting and resetting outputs 68 are made into L and the F/F34 is set and the F/F35-37 are reset. A signal 46 only out of signals 46-49 is made into H and TR53 only among transistors TR50-53 is turned on. Signals 1 and 4 are made into H and only the bit of a memory cell 25 is sensed. Next, a signal 67 is made into L by the next clock timing with signals 8 and 9, a signal 47 is made into H, the TR52 only is turned on, the bit of a memory cell 24 is sensed and respective senses of the designated address are executed by one sense circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor device, and particularly to a method for reading out a nonvolatile memory and a method for latching input data.

[Conventional technology]

FIG. 2 is a diagram of a conventional memory cell peripheral circuit.

In the figure, 22 to 25 are memory cells, 26 to 29 are selection transistors, 18 to 21 are sense circuits, and 30
-33 are PP switches, and 34-37 are D-type flip-flops for latching input data. Also 14-15
are the output signals of the sense circuits 18 to 21, and 42 to 4, respectively.
5 is a transfer gate, and 38 to 41 are inverters.

Next, the operation will be explained. During programming, signal 1 is "L", selection word 2 is "H", signal 3 is VPP, and signal 4 is "L". Signals 5 and 6 are each a high frequency clock of about 5 MHz and its inverted clock. Signal 7 is v
PP, signals 8 and 9 are a latch reading clock and its inverted clock, and the D-type F/Fs 34 to 37 output data inputs 10 to 13 at the falling edge of signal 8. At this time, if input data 10 to 13 are "H", VPP switch 3
0 to 33 are precharged, and the output of the switch is VPP.
becomes. Then, programming is performed by the potential difference between the gates of the memory cells 22 to 25 and their channels.

On the other hand, during reading, signals 1, 3.4 are each high
IL 11. The state becomes "H", and the memory cells 22 to 25 are in an "enhanced state" if data has been written, and are in a "depleted state" if data has been erased, and this state is determined by the sense circuits 18 to 21. do.

[Problem that the invention seeks to solve]

In such a conventional circuit, the D-type F/F of the long bone of the memory word
, V□ switch, and a sense circuit are required, and the number of circuits is large.In particular, the sense circuit has a large cell size, which has a large effect on the chip area.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a low-cost nonvolatile semiconductor device with a small number of circuits and a small chip size.

[Means for solving problems]

The non-volatile semiconductor device according to the present invention is provided with a shift register that creates time-division timing for reading and latches input data during writing, and senses each bit at a specified address using one sense circuit. This is done in a time-divided manner based on the following.

[Effect]

In this invention, a shift register is provided to create time-division timing for reading, read and write input data during writing, and one sense circuit senses each bit at a specified address based on the timing. Since this is done in time division, the number of circuits can be reduced and the chip size can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a nonvolatile semiconductor device according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 2 indicate the same parts,
15a is a single sense circuit that senses each bit and outputs the output signal 14a; 50 to 53 are transistors;
60 to 63 are gate circuits that constitute a shift register together with the D type F/Fs 34 to 37.

Next, the operation will be explained. During programming, when signal 67 is “H”, data inputs 10 to 13 are D type F/F 34 to
37. Hereinafter, the operation of the program is the same as in the conventional example.

Next, when reading, first the cent and reset output 68 is set to 'L'.
”, D type F/F34 is cent, D type F/F35 ~
37 is reset. Therefore, only the signal 46 among the signals 46 to 49 becomes "H", and the transistors 50 to 53
Of these, only Tr53 is turned on.On the other hand, signal 1
, 4 also become "H", and in the end, only the bit of memory cell 25 can be sensed. Next, at the next clock timing according to signal 8.9, if signal 67 is "L", signal 47 becomes "H", only transistor 52 is turned on, and only the bit of memory cell 24 is sensed. In this way, signal 6
If 7 is “L”, D type F/F is activated by the clock of signal 8.9.
As a result of 34 to 37 shifting the data in a ring shape,
Only one of the transistors 50 to 53 is turned on, so that each bit can be sensed in a time-division manner.

In this way, in this embodiment, the shift register for creating time-division timing for reading and latching input data for writing is connected to the D-type F/Fs 34 to 37 and the gate circuit 60.
63, each bit can be sensed in a time-division manner using a single sense circuit 15a, and the number of circuits can be reduced and the chip size can be reduced.
This makes it possible to reduce the price.

In the above embodiment, data input is input to the D-type F/F in parallel, but it may also be input serially. In this case, only the input of the D-type F/F 34 is input to the D-type F/F. The above-mentioned type of gate is required to select whether the output is from the type F/F 37 or not.

[Effects of the Invention] As described above, according to the present invention, a shift register is provided for creating time-division timing for reading and latching input data for writing, and senses each bit at a specified address in one. Since the sensing circuit performs the process in a time-division manner based on the above timing, the number of circuits can be reduced, and a nonvolatile semiconductor device with a small chip size and low cost can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a nonvolatile semiconductor device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional device. 22-25...Memory cell, 15a...Sense circuit, 34-37...D-type flip-flop, 60-63
...Gate circuit, 10-13...Input signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In an electrically rewritable non-volatile memory, a single sense circuit that senses each bit at a specified address in a time-sharing manner and multiple registers provided corresponding to each of the above bits are used. What is claimed is: 1. A non-volatile semiconductor device comprising: a shift register that creates the above-mentioned time-division timing during reading and latches input data during writing.