JPS63316396A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make it possible to use a semiconductor storage device also as a RAM and a variable length shift register by adding an address counter, a coincidence detecting circuit, an address selector, an address change detecting circuit, and an external clock terminal for shifting up the address counter to reference RAM constitution. CONSTITUTION:The address counter 2, the coincidence detecting circuit 3, the address selector 9, the address changing circuit 8, and the external clock terminal for shifting up said address counter 2 are added to the reference RAM constitution, and when the external clock terminal is set up to '0' and an address signal is impressed on an external address terminal 10, the constitution is driven as a RAM. When a clock signal is impressed on the external clock terminal, the device is driven as shift registers with 1-2<m> optional length corresponding to 1-2<m> optional binary values set up on the terminal 10. Consequently, a semiconductor storage device having high using efficiency can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to RAM (Random Access Memory)
The present invention relates to a semiconductor memory device that can selectively use the function of the variable-length shift register and the function of the variable-length shift register as necessary.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of a variable length shift register that has already been filed by the applicant of the present invention. R5 is a resettable row address counter, and 63 is a delay amount DA, ~DA, which is externally set as an m-bit binary value.
, and the address counter 62 outputs A1 to 80), and outputs a reset signal R3 to the address counter when a coincidence is detected, 64
6 is a decoder for row selection; 65 is a data input circuit;
6 is a data output circuit, 67 is a data input/output circuit 65.6
This is a control circuit that controls reading and writing of 6.

Next, the operation will be explained.

The operation when the value of the address counter 62 is cleared to 1 in the variable length shift register configured as described above and a one-stage delay is set from the outside will be described.

The memory cell array 61 reads out the contents of the row corresponding to address 1 according to the command from the control circuit 670, and then overrides the data DI in the same row in a focused parallel manner. The address counter 62 performs count amplification at the falling edge of the clock φ, and the decoder 64 takes in the outputs A, ˜A, of the address counter 62 at the rising edge of the clock φ, executes decoding, and specifies a specific row. The memory cell array 1 sequentially performs reading and writing from the value of the address counter 62 to the row specified by the decoder 64 according to instructions from the control circuit 67, and at the rising edge of the (l-1)th clock, the decoder 64 reads and writes the row specified by the decoder 64.
Since the value (l-1) of 2 is latched, the memory cell array 61 performs data read and write operations for the (j!-1)th row.

Then, when the (1-1)th clock φ falls,
The address counter 62 counts up, its output value becomes l, and the -number configuration circuit 63 sets (tlA,
-DA, and counter output A, ~A1 match, so -
The number output circuit 63 outputs the reset/node signal R3 and clears the address counter 62 to address 1.

Therefore, the address latched into data at the rising edge of the first clock φ is 1, and the memory cell array 61
reads the first data written in the first line,
Next, override the (1+1)th input data.

By repeating the above operations, a shift register with a delay of four stages (l≦2″) can be constructed.

[Problem that the invention seeks to solve]

The variable length shift register invented by the applicant mentioned above is configured as described above, and because it uses memory cells as storage devices, it achieves large capacity and low power consumption with a simple configuration. .

However, since the above-mentioned memory cells are used as shift registers and cannot be used as random access memories, there is a problem that usage efficiency is poor.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device that can be used both as a random access memory and as a variable length shift register.

[Means for solving problems]

In the semiconductor memory device according to the present invention, the delay amount setting terminal of the variable length shift register configured as described above is an external address terminal to which an address signal or a delay amount setting value is input, and an address input from the external address terminal is provided. The input signal of the external address terminal is fixed, and when the external clock is input, the address change detection circuit detects whether the input signal of the external address terminal changes, and the input signal of the external address terminal is fixed. and an address selector that outputs the input signal of the external address terminal to the decoder when no clock is input.

[Effect]

In this invention, the address selector is controlled depending on whether or not the input to the external address terminal changes and whether or not an external clock is input, and either the address counter output or the input signal from the external address terminal is sent to the decoder. Since it is configured to switch output, it can operate both as a variable length shift register and as a random access memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a configuration diagram showing a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is an n-bit x 7-byte memory cell array, 2 is operated by an external clock φ, and is operated by a reset signal R3. resettable row address counter,
3 outputs the address data DAI ~ DA, which is set from the outside as an m-bit binary value, and the address counter 2 output CAI ~ CA, and when - defeat is detected, the output is sent to the address counter. a coincidence detection circuit that outputs a reset signal R8; 4 is a decoder for row selection;
5 is a data input circuit, 6 is a data output circuit, and 7 is a data input/output circuit 5.6 for reading.

This is a control circuit that controls writing. The control circuit 7 receives the external WE signal and outputs WE.

Outputs OE multiplied signal. Note that the WE signal is a write enable signal, and during the period when WE is “1”, the input data DI
t~D1. is set in a writable state to the memory cell array 1 via the data input circuit. Also, it is an OE multiplication signal output enable signal, and during the period of OR input 13, the store information of the memory cell array I is sent through the data output circuit.
Make it readable. Further, 8 is an address change detection diagram fm, and 9-1 to 9-m are address selector circuits. The address selector circuit 9 is a circuit that selects and passes either address data DA + to DA inputted from the outside and address counter 2 outputs CA, -CA. Reference numeral 10 denotes an external address terminal, into which an address signal is input when the present embodiment is used as a RAM, and a terminal for setting a set delay amount when used as a variable length shift register.

FIG. 2 is a diagram showing an embodiment of the coincidence detection circuit 3 in FIG. Launch circuit, X0RI-XOR, which latches CA 4 with clock φ.

are the externally set address data DA held by the latch circuit 21 and the output CA of the address counter 2! An XOR gate with inputs, NOR is the above-mentioned XOR, -XO
The m-input NOR gate receives the output of R, and R3 is the output of the NOR and is a reset signal.

FIG. 3 is a diagram showing an embodiment of the address change detection circuit 8 of FIG. 1, and in the diagram, DL! (1≦i≦m)
is external setting address data DA! A delay circuit that delays (1≦i≦m) by a predetermined time (about 10ns), TXOR
, ~TXOR, is an XOR gate that receives the above DA1 and delay data as input, and OR is the above TXORI~TXOR,
This is an m-input OR gate that receives the output of , and outputs an address change detection signal ATD.

FIG. 4 is a diagram showing an embodiment of one bit of the address selector circuit 9 of FIG. 1, where i is an integer value between 1 and m.

ANOR,1i, ANOR2t are NOR circuits that connect each output to the other input to create the RS latch circuit 1.
The external clock signal φ is input to the other input of ANOR1+, and the address change detection signal ATD is input to the other input of ANOR2. Also TG
1i is a transmission gate, and its gate electrode is connected to the ANOR1i output, its source electrode (or drain electrode) is connected to the external address data line DA, and its drain electrode (or source electrode) is connected to the selector output A1. TG2i is a transmission gate, and its gate electrode receives the A N OR2i output, and its source electrode (or drain electrode) receives the output CA of the address counter 2.
1 to the drain electrode (or source electrode) and the selector output A! Concatenate.

In the semiconductor memory device configured as described above, a mode (mode I) in which it operates as a variable length shift register and a mode (mode (2)) in which it operates as a random access memory will be explained.

In mode I, external address data DA, ~DA,
is an m-bit binary fixed value that sets the amount of delay of the variable length shift register. A clock drift φ synchronized with data input is applied to the external clock terminal. Address counter 2 operates based on external clock φ and outputs address data CA, -CAI. Also, since the external address data DA, ~DA, are fixed values, the TXOR
.

Since each output of ~TXOR, is always "10", the address change detection signal ATD is "0". Regarding the RS latch 11-3 of the address selector 9-i, ATD is "0".
By constantly applying external clock φ at
NOR1! The output of the transmission gate T G is "O'" and the output of ANOR21 is "L".
1! is off, transmission game) TG21
turns on.

Therefore, the address counter output CA, is selected, and the address counter outputs CA, ~CA, which are shifted up by the external clock φ, are input to the decoder 4.

In the semiconductor memory device configured as described above, when the value of address counter 2 is cleared to 1 and a two-stage delay is externally set (i.e., a binary value consisting of externally set address data DA, ~DA, ).

External clock signal φ, external WE signal, input data DI
t~D1. is input according to the timing chart shown in FIG. 5(a).

The memory cell array 1 reads out the contents of the row corresponding to the address l according to the command from the control circuit 7, and then overrides the data DI in the same row in bit parallel. The address counter 2 counts up at the rising edge of the clock φ, and the decoder 4 outputs the outputs CA and -CA of the address counter 2.

, perform decoding, and specify a specific line.

The memory cell array 1 sequentially performs reading and writing from the value of the address counter 2 to the row specified by the decoder 4 according to the command from the control circuit 7. At the rising edge of the (71-1)th clock, the decoder 4 reads the value of the address counter 2. Since the value (A-1) is decoded, the memory cell array 1 reads data for the (Jt-1)th row,
When the first clock φ that performs a write operation rises, the address counter 2 counts up, and when its output value reaches l, the -number output circuit 3 sets the set value D.
Since A t~DA and the counter output CA +~CA are defeated, the m number of X's in FIG. 2 (7) XOR, -XOR,
Since all the OR outputs become ``L'', the reset signal R3, which is the output of the NOR using these as inputs, becomes 6H'', clearing the address counter 2 to address l.

Therefore, the address input to the decoder at the rising edge of the first clock φ is l, and the memory cell array 1 is 1
The first data written in the row is read, and then the (J+1)th input data is overwritten in the first row.

By repeating the above operations, it is possible to configure a shift register with a delay of one stage (l≦2'''). Since l is an externally set value by Yura, it can be set to any length ≦ as requested by the user.
21) shift register can be constructed.

Next, mode (2) in which the memory operates as a RAM will be explained.

The external clock terminal is fixed at "O" and no clock is applied. Therefore, the address counter 2 does not operate, and the external address data D A m to DA1 serve as address inputs to the RAM. When any one of DA and ~DAI changes from 1'' to 0 or from 0 to 1, any of the outputs of TXOR and ~TXOR in FIG. Accordingly, the output A of the address change detection circuit 8
TD also outputs a positive pulse. Address selector circuit 9
Regarding the RS latch 11-1 of -i, the external clock is fixed at '0' and the ATD pulse is applied every time the address changes, so the output of ANORIs is always '1'.
', the output of ANORZ5 becomes "0", so the transmission gate TG1+ is turned on, and T G 2 +
turns off. Therefore, external address data DA! is selected and input to the decoder 4.

In the semiconductor memory device configured as described above, the fifth
It is clear that it can be operated as a general-purpose random access memory by inputting the address decoder DA,=, the external WE signal, and the input data DI,=, according to the timing chart shown in Figure (b). .

Note that the memory cell array used in this embodiment may be composed of static memory cells or dynamic memory cells, but the operation of these memory cell arrays is well known to those skilled in the art. Therefore, detailed explanation will be omitted.

As described above, in this embodiment, the standard RAM configuration includes the address counter 2, the -number output circuit 3, the address selector 9, and the address change circuit 8.

Add an external clock terminal for shifting up the address counter 2, fix the external clock terminal to “O”,
When an address signal is applied to external address terminal 10, RA
When a clock signal is applied to the external clock terminal, 1 to 1 set to the external address terminal 10
Since it is configured to operate as a shift register of any length from 1 to 2'' in response to any binary value up to 2'', it is possible to obtain a semiconductor memory device with high usage efficiency. In particular, from the user's perspective, the configuration of the present invention is a simple configuration in which one external clock terminal is added to the standard pin specifications of the RAM.

For example, a static RA with 8 words x 8 bits
In the case of M, it is a 28-pin JEDEC standard pin arrangement, and N
By using the first pin, which is the C (No-Connection) pin, as an external clock signal used in the configuration of the present invention, it has the function of a RAM that complies with the JEDEC standard pin layout, and has 1 to 8.192 stages. It is possible to provide a semiconductor memory device that also has the function of a variable-length shift register that can vary the number of delay stages, and its effects are very large.

In the above embodiment, the one-loss detection circuit 3 is constructed of an XOR gate and a NOR gate, but the same operation can be achieved by replacing the XOR gate with an XNOR gate and replacing the NOR gate with an AND gate.

In addition, in the above embodiment, the memory cell array is n bits×
Although the configuration has been described as follows, it may be configured as n bits×R rows×J columns.

In that case, the decoder 4 is composed of R row decoding means and three column decoding means.

Furthermore, although the data input terminal 5 and data output terminal 6 in the above embodiment are configured separately, the so-called I10
The common configuration may be such that the data input terminal and the data output terminal are shared.

〔Effect of the invention〕

As described above, according to the present invention, a standard RAM configuration includes an address counter and a number output circuit.

By adding an address selector, an address change detection circuit, and an external clock terminal for shifting up the address counter, it is configured so that the RAM function and variable length shift register function can be used separately as necessary. This has the effect of providing a highly efficient semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of a coincidence detection circuit used in the semiconductor memory device of FIG. 1, and FIG. FIG. 4 is a diagram showing an embodiment of the address change detection circuit used in the semiconductor memory device shown in FIG.
Figure 6 is a timing diagram for detailed explanation of the present invention.
The figure shows a conventional variable length shift register. 1 is a memory cell array, 2 is an address counter, 3 is a coincidence detection circuit, 4 is a decoder, 8 is an address change detection circuit, 9 is an address selector, and 10 is an external address terminal.

Claims (1)

[Claims] (1) An external address terminal into which an address signal or delay amount setting value is input, a 2^m×n bit memory cell array, an address counter operated by an external clock, and the output of the address counter and the amount of delay from the outside. A match detection circuit that detects a match with a set value and outputs a reset signal to the address counter when there is a match; A decoder that outputs to the memory cell array, an n-bit input buffer and an output buffer connected to the memory cell array, and a control circuit that controls the input/output buffer.Whether or not the address input from the external address terminal has changed. The input signal of the external address terminal is fixed, and when the external clock is input, the address change detection circuit detects the output of the address counter.
A semiconductor memory device comprising: an address selector that outputs the input signal of the external address terminal to the decoder when the input signal of the external address terminal changes and the external clock is not input.