JPS6369097A - Shift register - Google Patents

Abstract

PURPOSE:To obtain a shift register in which various data shift actions can be possible by connecting an analog switch driven by a pair of prescribed clocks through an inverter and a pair of analog switches directly between a latching circuit and first and second nodes and connecting mutually a section between two pairs of switches. CONSTITUTION:When the data shifting from a first input/output node 19 to a second input/output node is executed, the clock of three phases is used in which clocks phi1 and f5 are made into a second phase clock and phi2 is made into a third phase clock. The input data of the node 19 are inserted and inverted through first and third analog switches 11 and 13 to a latching circuit 15 by a first phase clock. Next, by the second phase clock, the data are latched at the circuit 15, temporarily stored, and the data are inverted by an inverter 18 and inputted to a switch 14. Next, by the third phase clock, the output of the switch 14 is outputted through the switch 12 to a node 20. In the same way, the various types of the data are shifted.

Description

Detailed Description of the Invention [Purpose of the Invention (Industrial Field of Application) The present invention relates to a shift register provided in a temporary storage circuit in a digital signal processing circuit, and particularly relates to a shift register capable of bidirectional data shifting. Regarding bit shift registers.

(Prior Art) A conventional 1-bit shift register formed in an MO8 integrated circuit was constructed as shown in FIG. That is, between the data input node 31 and the data output node 32, a first clocked inverter 33, an input latch 34,
A second clocked inverter 35 and an output latch 36 are connected in cascade. A third clocked inverter 38 is connected between the output end and the input end of the inverter 37 to form a loop in the input latch 34, and similarly, the output latch 36 is connected to the output end of the inverter 39. A fourth clocked inverter 40 is connected between the input terminal and the input terminal to form a loop. The clocks used are the input clock φ and the clock 1 which is inverted by the input clock φ.

The clock φ is the second clock φ. The inverted clock φ is supplied to the third clocked inverter 35 and 38, and the inverted clock φ is supplied to the @1.
It is supplied to a fourth clocked inverter 33.40.

In the above shift register, the data input node 31
The input data Din of is inverted by the first clocked inverter 33 at the timing of the inverted clock φ, and then inverted again by the second clocked inverter 35 while being taken into the input latch 34 at the timing of the clock φ. This causes the output latch 36 to output the signal. Then, at the timing of the next inverted clock 1, the output latch 36 outputs data D. Latch ut and continue outputting output data.

By the way, in the above conventional shift register, the data input node 3 and the data output node 32 exist independently, and data is shifted in one direction from the input node to the output node, and the data input/output node is shared. Bidirectional data shifting is not possible. The output latch 36 also connects the inverter 39 and the clocked inverter 4.
Since the configuration is such that the data is output while looping with 0, the potential on the output side changes for some reason while outputting data and exceeds the threshold of the clocked inverter 40 of the output latch 36 even momentarily. If this happens, the logic level of the output data will be inverted, and this inverted data will continue to be held and output.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem in which the logic level of output data is reversed due to the influence of changes in the output side potential during data output. , it is possible to prevent level inversion of the output data due to the influence of the change in the output side potential, and also to perform bidirectional data shifting between two input/output nodes, input/output of data from one input/output node, etc. The object of the present invention is to provide a shift register capable of performing various data shift operations.

[Configuration of the Invention (Ninth Means for Solving the Problem) The shift register of the present invention has a first input/output node and a second input/output node.
A first analog switch and a second analog switch each controlled by a clock are connected in series between the input/output nodes of the above, and a third analog switch controlled by each clock is connected in series to the interconnection point of the two analog switches. One end of each of the switch and the fourth analog switch is connected to the other end of the third analog switch, the input end of a latch circuit including an inverter and a clocked inverter connected in a loop is connected, and the output end of this latch circuit is connected to the other end of the third analog switch. and the other end of the fourth analog switch.

(Function) According to the above shift register, by controlling the timing of each clock applied to the analog switch and clocked inverter, bidirectional data shifting is performed between two output cathodes, and one input/output node Various data shifting operations such as inputting and outputting data from In this case, by keeping the analog switch at the final stage in the OFF state while data is in operation, it becomes possible to shift the data at the correct logic level without being affected by changes in the output side potential. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a 1-bit shift register formed in an MO8 integrated circuit, and 11 to 14 are first analog switches using, for example, a 0MO8 transfer gate, which are turned on when a clock is input. A fourth analog switch, 15 is a latch circuit in which a clocked inverter 17 is connected between the output end and the input end of an inverter 16, 18 is an inverter, and these are the first input/output node 19 and the second It is connected to the input/output node 2v as follows. That is, the first analog switch 11 and the second analog switch 12 are connected in series between the first input/output node 19 and the second input/output node 20. Further, the third analog switch 13, the latch circuit 15, the inverter '1B, and the fourth
analog switches 14 are connected to form a loop. The connection point between the analog switch 11 and the second analog switch 12 of the Kamisuki WIl is connected to the connection point between the third analog switch 13 and the fourth analog switch 14. Note that clocks φ1 to φ4 are applied to the first to fourth analog switches 11 to 14, respectively, and clock φ is applied to the clocked inverter 17 of the latch circuit 15.

Next, the operation of the shift register will be explained.

(1) When data is shifted from the first input/output node 19 to the second input/output node 20, the clock φ1. φ
, is the first phase clock, and the clock φ4. B where φ is the second phase clock and clock φ is the third phase clock.
A fi-class (3-phase) clock is used. As a result, the input data D1n of the first output canode 19 is input to the latch circuit 15 via the first analog switch 11 and the third analog switch 13 due to the first phase clock and is inverted. Next, the data is latched by the latch circuit 15 and temporarily stored by the second phase clock, and this latched data is inverted by the inverter 18 and then input to the fourth analog switch 14. Next, the third phase clock causes the output of the fourth analog switch 14 to be output to the second input/output node 20 via the second analog switch 12. According to the data shift operation described above, after data is shifted to the stage before the final output stage (second analog switch 12) (fourth analog switch 14), the data is output by the final clock (third phase clock). , even if the output side potential changes during data shift operation,
The level of the output data will not be reversed due to this influence.

(2) When data is shifted from the second input/output node 20 to the first input/output node 19, the clock φ8
．． φ is the first phase clock, and clock φ4. Three types of clocks (three phases) are used, in which φ is the second phase clock and clock φ is the third phase clock. by this,
The input data Din of the second input/output node 20 is input to the latch circuit 15 via the second analog switch 12 and the third analog switch 13 by the first phase clock and is inverted. Next, the data is latched by the latch circuit 15 and temporarily stored by the second phase clock, and this latched data is input to the fourth analog switch 14 after being inverted by the inverter J8. Next, the third phase clock causes the output of the fourth analog switch 14 to be output to the first output canode 1-9 via the first analog switch 11. According to the above data shift operation, data is shifted to the previous stage (fourth analog switch 14) of the final output stage (first analog switch 11), and then data is output by the final clock (third phase clock). Therefore, even if a change occurs in the output side potential during the data shift operation, the level of the output data will not be reversed as a result of the change.

(3) When performing a data shift from the first input/output node 19 to the second input/output node 20 as in the conventional example, first, the clock φ1. φ8. φ, are turned on at the same time, and then the clock φ8. φ3 is turned off and the clock φ1. φ4
Just turn it on.

(4) When taking in data from the first input/output node 19, temporarily holding the data, and outputting this data from the first input/output node 19 again, first clock φ1
．． φ3. Simultaneously turn on φ, the first input/output node 1
9 input data D1n is input, then the clock φ is turned off to temporarily hold the data, and then the clock φ4 is input.
The above data can be output by turning on.

Even during the operations described in (3) and (4) above,
Since the analog switch in the output path is in the off state before data is output, even if the output side potential changes, it will not be affected.

Next, as an application example of the shift register of the above embodiment, the shift register SR is connected to a memory circuit as shown in FIG. Output node 20 is connected to memory cell array 22
The operation when connected to is explained below. When writing data to the memory cell array 22 from the data line 21, the above (
As described in 1), data is shifted from the first input/output node 19 to the second input/output node 20. When reading data from the memory cell array 22 to the data line 2, data is shifted from the second input/output node 20 to the first input/output node 19 as described in (2) above.

[Effects of the Invention] As stated above, according to the shift register of the present invention, data can be shifted at the correct logic level without being affected by changes in the output side potential during data shift operation, Furthermore, various data shifting operations are possible, such as bidirectional data shifting between two input/output nodes and data input/output from one input/output node.

[Brief explanation of the drawing]

Fig. 1 is a logic circuit diagram showing an embodiment of the shift register of the present invention, Fig. 2 is a configuration explanatory diagram showing an application example of the shift register of Fig. 1, and Fig. 3 is a logic circuit showing a conventional shift register. It is a diagram. 11 to 14...first to fourth analog switches, 15
...Latch circuit, 16.18...Inverter, 17
... Clocked inverter, 19... First input/output node, 20... Second input/output node. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A first analog switch that is connected in series between a first input/output node and a second input/output node and is driven by a clock φ_1 and a second analog switch that is driven by a clock φ_2; A third analog switch driven by clock φ_3, a fourth analog switch driven by clock φ_4, and the other end of the third analog switch are connected to the interconnection points of the three analog switches. a latch circuit consisting of an inverter to which an input end is connected, a clocked inverter connected between the output end and the input end of this inverter and driven by a clock φ_5; and an output end of this latch circuit and the fourth analog and an inverter connected between the other end of the switch.