JPS6376198A - Shift register - Google Patents

Abstract

PURPOSE:To attain a stable shift action by connecting two inverters through two single channel MOS transistors, constituting a memory cell and connecting further through two single channel MOS transistors between the next step memory cells. CONSTITUTION:In a section II, at the section where a clock is H, Nch enhancement type MOS transistors (Nch TRs) 3, 4, 7, 8 and 20 are turned off by AND-OR gates 13 and 14 and an AND gate 15 and Nch TR 19 is turned on by an AND gate 12. In such a case, the information of a memory cell 2 held at the gate capacity of a CMOS inverter 2 is transferred through the Nch TR 19 to the gate capacity of a CMOS inverter 5. When a clock goes to L, the Nch TR 19 is turned off by the AND gate 12, the Nch by TRs 4 and 8 are turned on, therefore, the information of the memory cell 21 transferred to the gate capacity of the CMOS inverter 5 is stored to the gate capacity of a CMOS inverter 6 through the Nch TR 8. In short, the information of the memory cell 21 is shifted by one bit to a memory cell 22.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a shift register, which can stably perform bidirectional shifting operations without causing racing, and which is integrated with a small number of elements. This article relates to a shift register suitable for circuitization.

[Conventional technology]

Conventional shift registers use memory elements with a large number of elements, such as D-clip 70 tubes, as basic cells.

[Problem that the invention seeks to solve]

The conventional shift register described above uses a D-type flip-flop (hereinafter referred to as D) as a storage element for storing information.
F/F ) is often used, but D and
The F/F itself has a large number of elements, and when set and reset functions are added, the number of elements increases, resulting in a disadvantage that the area becomes large, especially when configured as an integrated circuit.

[Means for solving problems]

The shift register of the present invention has two inverters with their respective control lines as gate inputs.
The memory cells are all 1-bit memory cells connected through S transistors, and the connection between the memory cells is two single-channel MO8) whose gate inputs have control lines different from those described above. This is done through a register, and unlike conventional shift registers, it has an original content in that it is constructed using memory cells.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a memory cell used in the present invention, and FIG. 2 shows an embodiment of a shift register using the memory cell shown in FIG. 1 and operating on an l-phase clock. FIG. 3 is a timing chart for explaining the shift operation of the embodiment shown in FIG.

In FIG. 2, reference numerals 1, 2, and 5.6 are CMO8 converters constituting the memory cells 21 and 22;

8.19.20 is an Nch enhancement type MOS transistor (hereinafter abbreviated as NchTr); 9 to 11 are inverters for inverting the input signals of terminals 16 to 18;
2.15 is an AND gate, 13 to 14 are AND-OR gates, 16 is a shift enable terminal, and 17 is a forward direction/
The reverse direction shift switching terminal 18 is a clock terminal.

In Figure 3, in the section construction, AND gate 12.15
Since the output of is low level (abbreviated as below), Nch
Tr 19 and 20 are turned off. Also, the output of AND-OR game) 13.14 is No. 1 level (hereinafter abbreviated as H)
Therefore, NchTr3°4.7.8 is turned on. Therefore, the information stored in each memory cell is stably held and no shift operation is performed.

In section ■, when the clock is H, AND-O
fiN through R gates 13 and 14 and AND gate 15
chTr3, 4.7+8+20 is turned off, and the AND gate 12 is turned on. At this time, the information of the memory cell 21 held in the gate capacitor of the CMOS inverter 20 is transferred to the gate capacitor of the CMOS inverter 5 forming the memory cell 22 through the NchTr 19i. Then, when the clock becomes L, the AND gate 12 turns off the Nch Tr 19, and the AND-O
Since NchTr4 and NchTr8 are turned on by the R gate 14, the information of the memory cell 21 transferred to the gate 8 of the CMOS inverter 5 in the memory cell 22 is transferred to the NchTr
8 and is stored in the gate capacitance of the CMOS inverter 6. In other words, in the interval (3), the information in the memory cell 21 is shifted to the memory cell 22 by one bit.

Since L is input to the forward/reverse shift switching terminal in section ■, in the section where the clock is H, AND-O
Output 2 of R gate 13014 and AND gate 12>
To become EL, N ch Tr 3 r 4 +7.8
．． 19Vi is turned off, and the output of the AND gate 15 becomes H, so the Nch Tr 20 is turned on. At this time c = x
The information of the memory cell 22 stored in the gate capacitance of the IOS inverter 5 is transferred to the gate 8 of the CMOS inverter 2 forming the memory cell 21 through the NchTr 20. Then, when the clock becomes L, the AND gate 15 turns off the p Nch Tr 20, and the AND-O
Because the R gate 13 turns on [NchTr3°7,
Information of the memory cell 22 transferred to the gate capacitor of the CMOS inverter 2 in the memory cell 21 is stored in the gate capacitor i of the CN0S inverter 1 through Nch3. However, in section 1, there is a 1-bit shift, contrary to the case of section (2).

FIG. 4 is a circuit diagram of a 20th embodiment of the present invention.

In FIG. 4, a storage cell, a shift enable terminal, a forward/reverse shift switching terminal, and an inverter for inverting signals inputted from the two terminals are connected to a third inverter.
Although similar to the figure, in the second embodiment, the shift operation is performed by inputting two-phase clocks to terminals 27 and 28, respectively.

FIG. 5 is a diagram showing the timing at which the circuit in FIG. 4 operates. The principle of the shift operation is the same as in FIG. 3, so the explanation will be omitted. In this case, there is a slit in the two-phase clock Therefore, a more stable shift operation can be performed.

〔Effect of the invention〕

As explained above, the present invention connects two inverters to two
A storage cell is configured by connecting through two single-channel MOS transistors, and stable shifting without racing is achieved by connecting through two single-channel MOS transistors between the storage cell and the next-stage storage cell. A bidirectional shift register with a small number of elements can be constructed.

Furthermore, addition of set and reset functions can be realized by adding a few transistors.

[Brief explanation of the drawing]

FIG. 1 shows an example of a memory cell according to the present invention, and FIG. 2 shows the memory cell of FIG. Example 1 of the shift register according to the present invention used, FIG. 3 is a timing chart for explaining the operation of the shift register of FIG. 2, and FIG. 4 is a timing chart for explaining the operation of the shift register of FIG.
Embodiment 2 of the shift register according to the present invention using the memory cell shown in the figure, FIG. 5 is a timing chart for explaining the operation of the shift register of the fourth factor. 1.2, 5, 6...CMOS inverter, 3゜4.7, 8, 19.20...Nch encoder MOS) transistor, 9-11... ...Innokuichita, 12, 15, 23.26...AN
D gate, 13.14, 24.25...AND
-OR gate, 16...shift enable input terminal, 17...forward/reverse shift switching input terminal, 18°27.29...clock input terminal. Figure 7 L: Engineering j IL Column 3I21

Claims (1)

[Claims] In a shift register capable of transferring information bit by bit, the storage cells are arranged such that the input of a first inverter and the output of a second inverter are connected to each other, and the output of the first inverter and the input of a second inverter are connected to each other, respectively. A first single channel MOS transistor whose gate is inputted to the first control line is connected to a second single channel MOS transistor whose gate is inputted to the second control line. The input and output of the inverter in the next storage cell are connected to the output and input of the first inverter in the next stage storage cell, and the third and fourth single channel MOS transistors whose gates are respectively inputted to the third and fourth control lines. A shift register characterized in that it is connected through.