JP3019627B2 - Data retrieval device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data retrieval apparatus for retrieving data in a computer at high speed.

[0002]

2. Description of the Related Art As shown in FIG.
It comprises a central control circuit 2 and a central control storage circuit 6. Here, when performing a data search, data is read one by one from the central control storage circuit 6 and compared with the search data to search for sequentially matching data.

Therefore, when collating all data with search data, it takes a lot of time to read all data. For example, if 1 megabyte of data is processed at a calculation speed of 1 mips, (1) read address calculation , (2) reading, (3) comparison with search data, and (4) conditional branching, the search was repeated, and as a result, a search time of about 4 seconds was required.

[0004]

As described above, there is a drawback that the processing speed is slow when a calculation is repeated using a conventional electronic computer to repeat the association such as application to artificial intelligence.

[0005] An object of the present invention is to provide a data retrieval apparatus having a high processing speed, excluding such a conventional disadvantage.

[0006]

According to the present invention, there is provided a central control circuit which is connected to an address bus and a data bus and has a control signal terminal for outputting a data control signal, stores respective search data, and stores the search data. In a data search device comprising a plurality of dedicated circuits connected to an internal data bus by reading storage addresses of these search data, the dedicated circuit transmits data from the data bus to the control signal and the address bus. A search data storage circuit that stores the data in accordance with the address and outputs the data to the internal data bus, and compares the data in the internal data bus with the data stored in each storage circuit in accordance with each address specified in the address bus. And a plurality of unit circuits each outputting the address to the data bus.

[0007]

DETAILED DESCRIPTION FIG. 1 shows a block diagram of the computer of Kazumi施例of the present invention. In this embodiment, a dedicated circuit 1 described below for simultaneously reading and simultaneously comparing memories is connected to an address bus 3, a data bus 4 and a control signal 5 of a central control circuit 2, and a central control storage circuit 6 Also connect.

The dedicated circuit 1 includes a storage circuit 7, a buffer circuit 8, an address decode circuit 9, a comparison circuit 10,
It has a plurality of unit circuits 16 composed of a combination of a storage address output circuit 11 and a signal suppression circuit 17, and has a search data storage circuit 12, its address decode circuit 13, an address decode circuit 14 for a storage address data output command, and an internal data bus. 15 is formed. The storage address output circuit 11 is a circuit that outputs the storage address of the storage circuit 7 to the data bus 4.

The data terminal bundle of the storage circuit 7 is connected to the data terminal bundle of the buffer circuit 8, the other data terminal bundle of the buffer circuit 8 is connected to the data bus 4, and the data is transmitted to the storage circuit 7 via the buffer circuit 8. The data of the bus 4 is read and written. The input terminal bundle of the address decode circuit 9 is connected to the address bus 3, and the output terminal thereof is connected to the gate control terminal of the buffer circuit 8. An output terminal of the address decode circuit 13 is connected to a control terminal of the search data storage circuit 12,
The input terminal bundle of the search data storage circuit 12 is connected to the data bus 4. The output terminal bundle of the search data storage circuit 12 is connected to the first input data terminal bundle of each comparison circuit 10 via the internal data bus 15. The data output terminal bundle of the storage circuit 7 is connected to the second input data terminal bundle of the comparison circuit 10.

The comparison circuit 10 includes a search data storage circuit 12
Is compared with the value of the storage circuit 7, and when both match, a "comparison match" signal is output to the comparison result output terminal. The signal suppression circuit 17 includes a suppression signal input terminal 1
7-1 shows the suppression signal output terminal 1 of the preceding signal suppression circuit 17.
7-2, and the comparison circuit 10 is connected to the comparison result input terminal 19.
Connect the comparison result output terminal. The signal suppression circuit 17 includes a comparison result storage circuit 18, and sets the value of the comparison result storage circuit 18 to "comparison match" at the rising edge of the signal at which the signal value of the comparison result input terminal 19 becomes "comparison match". . The value of the comparison result storage circuit 18 is “comparison match”, or the value of “with suppression” is output to the suppression signal input terminal 17-1. The suppression signal output terminal 17-2 is connected to the input terminal of the buffer circuit 21, and its output terminal is connected to the wired OR circuit 22. Wired or circuit 2
2 connects the signals of all the signal suppression circuits 17 to the buffer storage flag terminal 23, and outputs the presence or absence of the storage circuit 7 having the same value as the search data. The output terminal of the address decode circuit 14 is connected to the control signal input terminal 20 of the signal suppression circuit 17.

When the memory address data output command address is output to the address bus 3, an address read signal is supplied from the output terminal of the address decode circuit 14. When the input signal to the suppression signal input terminal 17-1 is “no suppression” and the value of the comparison result storage circuit 18 is “comparison match”, the signal suppression circuit 17 performs comparison at the rising timing of the address read signal. The value of the result storage circuit 18 is "mismatch"
And the storage address output circuit 11 outputs the storage address of the storage circuit 7 to the data bus 4 at the same time. Thereby, the storage address of the storage circuit 7 having the same value as the search data is stored in the data bus 4.
Output to The central control circuit 2 stores data in each storage circuit 7 of the dedicated circuit 1 and also stores search data in a search data storage circuit 12.

Next, the central control circuit 2 confirms the output of the buffer storage flag terminal 23, outputs the address of the storage address data output command to the address bus 3, and outputs the storage addresses output from the storage address output circuit 11 in ascending order. It is configured to read data to the data bus 4.

[0013]

As described above, according to the present invention, the address of the storage circuit corresponding to the search data can be directly read, so that high-speed data search can be performed.

[Brief description of the drawings]

Block diagram of Kazumi施例of the present invention; FIG.

FIG. 2 is a block diagram of a conventional data search device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Dedicated circuit 2 Central control circuit 3 Address bus 4 Data bus 5 Control signal 6 Central control storage circuit 7 Storage circuit 8,21 Buffer circuit 9,13,14 Address decode circuit 10 Comparison circuit 11 Storage address output circuit 12 Search data storage circuit 15 the internal data bus 16 the unit circuit 17 signal suppression circuit 17-1 suppression signal input terminal 17-2 suppression signal output terminal 18 the comparison result storage circuit 19 a comparison result input terminal 20 a control signal input terminal 22 Wayadooa circuit 23 buffer storage flag pin

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/30 G11C 15/04

Claims (1)

(57) [Claims] 1. A central control circuit connected to an address bus and a data bus and having a control signal terminal for outputting a data control signal, storing each search data, designating the search data, and reading a storage address of the search data. And a plurality of dedicated circuits connected to an internal data bus, the dedicated circuit stores data from the data bus according to the control signal and the address of the address bus, and stores the data in the internal data bus. A search data storage circuit to be output, and data on the internal data bus are compared with data stored in each storage circuit in accordance with each address specified on the address bus, and when they match, the address is output to the data bus. And a plurality of unit circuits.