JPS6319858Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an address translation device, in particular, a physical address table corresponding to a continuous logical address space is prepared, and a series of physical address groups in the physical address table are held in an address translation management buffer. The present invention relates to an address translation device that accesses the address translation management buffer using a logical address when accessing a memory, and converts the logical address into a physical address.

In the virtual memory method, an address translation table is prepared to make a correspondence between a huge logical address space and a limited physical address space, and the logical address is converted into a physical address using this address translation table before accessing the memory. I try to do that.

For the sake of explanation, it is assumed that the address formats of logical addresses and physical addresses are as shown in FIG. In other words, the logical address is 8-31 bits representing 16MB of space, and the physical address is 10-31 bits.
Assume that 31 bits, or 4MB, of memory is implemented as real memory, and the size of the memory unit (page) is managed in units of 20-31 bits, or 4KB. Address translation from a logical address to a physical address is performed by converting the L part of the logical address to the P part of the physical address.

Here, FIG. 2 illustrates the logical address space and physical address space. The unit of memory is a page, or 4KB. As mentioned above, address translation ultimately involves establishing a correspondence between logical addresses and physical addresses on a page-by-page basis. According to the prior art, a table corresponding to logical addresses is prepared to manage physical addresses. However, as the logical address is expanded to represent a larger logical address space, this management table also becomes enormous and complex.

FIG. 3 shows a table for conversion management in the simplest case according to the prior art.
The size of this table is the entire logical address space, so it is very large. The implemented real memory, or physical address space, is much smaller than the logical address space. FIG. 4 shows a table that has been further improved. In other words, it is sufficient to have as many tables as the physical address spaces are shown. Note that here, since the focus is on the memory area for the table, detailed control information and the like are omitted and not considered. Let us now consider the case where the logical address is expanded to 0-31 bits and the physical address is expanded to 4-31 bits.

Figure 5 shows an example of the conventional address translation method, where the translation table is converted into a segment table (ST).
This method manages data in two stages: and page table (PT). According to this method, in order to obtain a physical address using the segment table (ST) and page table (PT), two
Since the read operation must be performed multiple times, it has the disadvantage that conversion takes time. Furthermore, as mentioned above, the number of conversion tables is enormous.

To this end, the above-mentioned problems are solved, and a logical address can be easily and quickly converted into a physical address, and a method for managing a huge physical address space in a huge logical address space is also provided. Furthermore, the present inventors have proposed an address conversion method for providing a means for realizing large-volume and high-speed access to such a huge memory space, as disclosed in Japanese Patent Application No. 162536/1986 (Japanese Patent Application Laid-Open No.
56-87281). This proposed address conversion method uses a page as a unit of a certain size of memory, and accesses the memory while performing address conversion for each page based on a predetermined logical address and physical address conversion table. In an information processing device, for a partial logical address space of interest that is smaller than the entire logical address space, a physical address table corresponding to consecutive logical address spaces is prepared, and a continuous logical address space consisting of a plurality of pages is prepared. A group of physical addresses corresponding to the address translation management buffer is held in an address translation management buffer, and when accessing the memory, the address translation management buffer is accessed using a logical address to convert the logical address to a physical address. be.

In other words, this address conversion method prepares a physical address table only for the contiguous logical address space of interest for a huge logical address space, reduces the table management and hardware required for conversion, and achieves high speed. It performs conversion.

FIG. 6 shows the concept of address translation using the above method. That is, consecutive partial spaces of the logical address space are made to correspond to the physical address space. In the figure, a solid line indicates an example of the correspondence between logical addresses and physical addresses in page units.

FIG. 7 shows the physical address table required at this time. In other words, by using only the physical address table corresponding to the physical address space,
It is possible to establish a correspondence with the continuous logical address space of interest.

FIG. 8 shows an example of an address conversion circuit according to the above method. In the figure, 1 is a logical address register, 2 is a physical address register that holds the converted physical address, and 3 is a physical address register created from a physical address table having the relationship shown in Figures 6 and 7 for high-speed address conversion. 4 is a comparison circuit, L is a logical page section, P is a physical page section, D is an intra-page address section, P' is a physical address, and l' is a part of the logical address. Note that since the size of the address translation management buffer 3 is made the same as the size of the physical address space, l', which is a part of the logical address, is required.

In FIG. 8, the contents of the address translation management buffer 3 are read out using the lower part of the logical page portion L of the logical address register 1 as an address. and,
The upper part of the logical page part L and the read l' are compared by the comparison circuit 4, and if they match, the page is read out.
Set P' in the physical page portion P of the physical address register 2.

By the way, in the general address translation method,
When registering the contents of the physical address table on the memory (segment table ST and page table PT in the example shown in FIG. 5) in the address translation management buffer on the hardware, a complicated procedure is required.

The present invention focuses on the continuity of the physical address table in the address conversion method proposed above, and
The purpose is to enable registration to an address translation management buffer to be performed quickly and easily using less hardware. Therefore, the present invention prepares a physical address table that corresponds to a part of consecutive logical address spaces in a logical address space that is larger than the physical address space, and manages address translation for a series of physical addresses in the physical address table. In an address translation device that converts a logical address into a physical address by accessing the address translation management buffer using a logical address when accessing the memory, a logical address indicating the start of an entry to be taken out from the physical address table. , a means is provided for instructing a physical address where a logical address table entry corresponding to the logical address indicating the head exists, and for detecting an increment in the counter of an address accessing the address translation management buffer, and the address translation management When creating a buffer, the contents of the physical address table specified above are sequentially read out, and from the address position of the address conversion management buffer indicated by the lower part of the logical address specified above, the corresponding physical address and the logical address specified above are determined. By registering the upper part of the address and detecting the carry, from then on, the value of the upper part of the specified logical address + 1 is added to the upper part of the logical address in the address conversion management buffer. It is characterized in that it is also registered.

The present invention will be explained below with reference to the drawings. FIG. 9 is a block diagram of the registration control unit of the address translation management buffer according to the embodiment of the present invention. In the figure, 10 is a logical address register, and the logical address indicated by the head of the entry to be taken out from the physical address table in the memory is shown in FIG. , 11 is a physical address register that holds the physical address where the physical address table entry corresponding to the logical address indicating the start is present, 12 is an address translation management buffer, and 13 is to the address translation management buffer 12. Address counter for access; 14 is a write register that holds data registered to the address conversion management buffer 12; 15 and 16 are +1 circuits; 17 is a carry for detecting the carry of the address counter 13 and one cycle of the address counter 13. - Completion detection circuit.

The operation of FIG. 9 is as follows. First, set the logical address indicated by the beginning of the entry to be fetched from the physical address table in memory in the logical address register 10, and set the physical address in the physical address register 11 where the physical address table entry corresponding to the value of the logical address register 10 exists. Set. The physical address to be set can be obtained from the information at the time of creation of the physical address table (for example, from what address to what address of the logical address was expanded on the physical address, etc.). Then, the lower bits of the logical page section in the logical address register 10 are sent to the address counter 13 (in the illustrated example, the 5th to 11th bits b)
is set, and the upper bits (0th to 4th bits in the illustrated example) of the logical page part in the logical address register 10 are set to a part (logical address part) of the write register 14.
Set bit a). write register 14
The contents of the physical address table read by the physical address register 11 (Pb in the illustrated example) are set in the remaining portion (physical address field).

In this state, the first write operation is performed, and the upper bit a of the logical page and the physical address Pb are written to the address b of the address translation management buffer 12.
Store pairs of . Next, the +1 circuit 15 increments the contents of the address counter 13 by +1. At the same time, the content of the next entry in the physical address table (here, Pb+1) is read out using the address in which the value of the physical address register 11 is increased by 1, and is set in the physical address section of the write register 14. Note that the logical address portion of the write register 14 is not changed unless a carry of the address counter 13, which will be described later, is detected. As a result, in the second write operation, the pair of the upper bit a of the logical page and the physical address Pb+1 is stored at the address b+1 of the address translation management table 12. Thereafter, write operations are performed sequentially in the same manner, and when the upper bit a of the logical page and the physical address P127 are stored in the final address 127 of the address conversion management table 12, the address counter 13 causes a carry. Its content will be "0". This carry is detected by the carry/end detection circuit 17, and the carry/end detection circuit 1
7 controls the +1 circuit 16 and writes the write register 14
Let the upper bit a of the logical page be a+1. As a result, the next write is performed to the starting address 0 of the address translation management buffer 12, and a+1 is stored in the logical address field of the address translation management buffer 12. In addition, in the physical address field of the address translation management buffer 12, the physical address P1 in the next entry of the physical address table entry holding the physical address P127 is stored.
28 is stored. Thereafter, write operations are performed in the same manner while increasing the value of the address counter 13 again. And address counter 13
When the value of is changed from the initial set value b to b-1, after writing to address b-1, the carry/end detection circuit 17 detects the end of writing and stops the write operation. By performing the write operation in this way, the logical address section from address 0 to address b-1 of the address conversion management buffer 12 has a
+1 is stored, and a is stored in the logical address section from address b to the final 127th address.

Note that while using the address translation management buffer created as described above, if it becomes necessary to access another logical address that is not registered in the buffer, the logical address is stored in the logical address register 12. All you have to do is set it and perform the same process as above. Furthermore, if the other logical address is a logical address that does not exist in the physical address table, perform so-called pacing to change the physical address table, and then change the physical address table to the address translation management buffer in the same way as above. All you have to do is register.

FIG. 10 shows an example of how a series of physical addresses in a physical address table having 256 entries is stored in an address translation management buffer having 128 entries. In Figure 10, the 50th to
When storing the 177th entry to the address translation management buffer, the 50th to 50th entries of the physical address table
The 127th entry is stored in the 50th to 127th entries of the address translation management buffer, and the 128th to 177th entries of the physical address table are stored in the 0th to 49th entries of the address translation management buffer. Here, the 0th address of the physical address table is
The values of the 0th to 4th bits of the logical address register shown in FIG. 9 differ by 1 between the logical address corresponding to the 127th entry and the logical addresses corresponding to the 128th to 255th entries, and the latter has a larger value than the former. for that,
When storing the part shown in FIG.
As explained in the embodiment shown in the figure, the logical address part of the address translation management buffer is incremented by 1. In the embodiment, the physical address table has 256 entries and the address translation management buffer has 128 entries, but in a system with a larger memory space, for example, the physical address table has 4K entries and the address translation management buffer has 256 entries. It has a value such as entry.

As described above, according to the present invention, in an address translation device that prepares a physical address table corresponding to a continuous logical address space and holds a series of physical address groups in the physical address table in an address translation management buffer, Detects a digit stop in the address counter of the conversion management buffer,
At this time, I added 1 to the upper part of the logical address and wrote it to the address translation management buffer, so
With a simple configuration, the registration operation to the address translation buffer can be performed continuously at high speed.

[Brief explanation of the drawing]

Figure 1 is an example of the address format of a logical address and physical address, Figure 2 is an example of a logical address space and physical address space, Figures 3 and 4 are conventional examples of address translation management tables, and Figure 5 is a conventional example of an address translation management table. An example of an address conversion method, FIG. 6 is a diagram showing the concept of the address conversion method on which the present invention is based, and FIG. 7 is a diagram showing the concept of the address translation method on which the present invention is based. 8 is an example of a physical address table according to an embodiment of the present invention, FIG. 9 is a block diagram of a registration control unit of an address translation management buffer according to an embodiment of the present invention, and FIG. FIG. 6 is a diagram illustrating an example of a storage mode when the contents of a physical address table are held in an address translation management buffer. In FIG. 9, 10 is a logical address register, 11 is a physical address register, 12 is an address translation management buffer, 13 is an address counter,
14 is a write register, 15 and 16 are +1 circuits,
17 is a carry/end detection circuit.

Claims (1)

[Claims for Utility Model Registration] A physical address table corresponding to a portion of consecutive physical address spaces is prepared in a logical address space larger than a physical address space, and a series of physical addresses in the physical address table are used as addresses. An address translation device that stores an address in a translation management buffer, accesses the address translation management buffer using a logical address when accessing memory, and converts a logical address into a physical address,
Instructs the logical address indicating the head of the entry to be extracted from the physical address table and the physical address where the logical address table entry corresponding to the logical address indicating the head exists,
2), an address counter 13 for accessing the counter, a means 17 for detecting a carry of the counter, a register (14a) for holding the upper part of the logical address, and a means 16 for incrementing the logical address by 1 are provided. In creating , the contents of the physical address table are sequentially read from the specified physical address 11, and from the address position of the address translation management buffer indicated by the lower part (10b) of the specified logical address 10,
By registering the corresponding physical address (14 Pb) and the upper part (14 a) of the logical address specified above, and detecting the above carry 17, from then on, the logical address in the address translation management buffer is The value of the upper part (a of 10) of the specified logical address + 1 is registered in the upper part position of the logical address specified above, and the address translation pair is registered in the address translation management buffer from the physical address table set in advance by the above procedure. An address translation device characterized by setting.