JPH069038B2 - Direct memory access controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access (hereinafter referred to as DMA) control device for high-speed data transfer in an information processing device such as a minicomputer or a microcomputer. In particular, the present invention relates to a DMA controller having a function of searching a relational database structured in a table format at high speed.

[Prior Art] FIG. 3 is a diagram for explaining names of respective parts of a relational database structured in a table format. # 1, # 2, ... Are the number of lines, the number of lines is the number of records, each line is a record, and the length L of the record is the record size. Each column is called a field, and the length D of each field is called a field size. In such a database, a process of selecting data of a specific field (displayed by hatching in the figure) in the record by referring to the value of the field as shown in the figure, for example, employee number, name, age, address, etc. Age is 3 from employee records with fields
It is necessary to perform a search process to select those over the age of five.

Conventionally, such processing is performed by software of a general-purpose processor. That is, when accessing specific field data in a record in which fields are linked by pointers, when the access from one field data A to (A + D + 1) is completed, the field address (A + L) of the next record is set. Calculate and retrieve the field data one after another. Compare the contents in order,
The database processing operation such as saving the result in another address was executed finely.

[Problems to be solved by the invention]

When checking the value of a specific field in a structured database in a table format and extracting the matched records, the conventional general-purpose processor software calculates the field address to be accessed one after another using a pointer, and Since the process of comparing the constituent data one after another (content retrieval) is performed by general-purpose hardware, there is a problem that detailed programming is required, execution takes time, and high performance is not achieved. Also,
DM already as a means to speed up only data access
There was an A control device, but there was the problem that only data with consecutive addresses could be accessed. Further, there is also a problem that finding out a matched record cannot be dealt with because the DMA does not have a means for comparing data strings.

[Means for solving problems]

The DMA control device of the present invention comprises: a first counter in which the first setting data is set in synchronization with a first end signal and changes by a unit number in synchronization with a data read signal; a first register; A first adder that outputs the first setting data by adding the value of the first register to the output value of the instrument, a second counter that changes by the number of units in synchronization with the data write signal, and a second register, When the data read signal is calculated and the set value of the second register is completed, the third counter that generates the first end signal and returns to the initial state, and the first end signal is counted and the preset value is completed. And a fourth counter for generating a second end signal, data string comparing means for comparing a series of data strings to be read with registered data strings, and a gate circuit for selecting the output of the data string comparing means. Specify the operation of this gate circuit A third register having a DMA processing function and a data read signal with the content of the first counter as a read address, and a data write signal with the content of the second counter as a write address when the output signal of the gate circuit is generated. And a control circuit for outputting a signal and writing the contents of the fourth counter.

[Action]

Since the update value of the address counter corresponds to the database access structured in the table format, the DMA control device of the present invention reads out a specific field of such a database at high speed, and has a built-in data string comparison means. Real-time data string comparison can be performed with, which enables high-speed search of a specific field in a record.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a DMA controller according to the present invention. In this figure, 1 is a second counter, 2 is a first register, 3 is a first counter, 4 is a first adder, 5 is a fourth counter, 6 is a second register, and 7 is a third counter. , 8 is a data string comparing means, 9 is a mode register, 10 is a gate circuit, and 11 is a control circuit.

The control circuit 11 outputs a HOLDREQ signal to the CPU when the DMAREQ command is input from the CPU,
The operation starts when the CK signal returns.

When inspecting a field to find a matching record,
The control circuit 11 outputs the read address of the field stored in the first counter 3 to the address bus, and outputs the data read signal (read). While reading each field, the read address is increased by one address in synchronization with the data read signal (read). Before each field is accessed, the field length D is set in the third counter 7 from the second register 6, and this is subtracted by one address in synchronization with the data read signal (read) to zero. Then, the carry signal is output as the first end signal, and the end of reading of one field included in the record is known.

The distance L between the records is set in the first register 2, and the first adder 4 adds this to the output of the first counter 3 and outputs it as the setting data of the first counter 3. This setting data is set in the first counter 3 in synchronization with the first end signal. Thus, the target field of the next record can be accessed.

For example, if it is set that the specific field of one record is the address A and the distance between the records is L, the specific field of the next record starts from the address (A + L). Third counter 7 for holding field length D
Data of a specific field is A while the countdown
It is read from the address. After that, the address jumps to the address (A + L), and the field length D is reset in the third counter 7. When the contents of the counter 7 are counted down, the field data at the address (A + L + D-1) is read out. The above is repeated by replacing (A + L) with (A + 2L).

In this way, the data retrieval of the fields read one after another is processed by comparing with the data string registered in the data string comparing means 8 and outputting the large, small, equal, or the like. The gate circuit 10 selects the output of the comparison means 8 according to the designation of the mode register 9 from the read or the write and inputs it to the control circuit 11. By this input, the control circuit 11 outputs the content of the second counter 1 (the storage address of the match data) as a write address, and writes the content of the fourth counter 5 (record number) by a write signal (write). The content of the second counter 1 is incremented by one address in synchronization with this.

Initially, the number of records included in the database is set in the fourth counter 5. This is subtracted by one address by the first end signal output from the third counter 7, and each record can be identified. When this becomes zero, the carry signal is output from the fourth counter 5 as the second end signal, and the operation ends.

FIG. 2 is a block diagram of an embodiment of the data string comparison means 8 used in FIG. This is done by comparing a register 21 that stores a data string (A, B, C) to be compared, a counter 7 that gives an address to this register 21, an input data unit, and an output of the register 21. , Small, equal ”and a register 23 for a partial match signal which holds the output of the comparator 22 until it can be confirmed whether all the bits match or not and sequentially inputs it to the comparator 22 at the next data input timing. It consists of and.

This counter 7 is the same as the third counter 7 of FIG. 1 for counting the field length, and the data string (a, b,
The data string (A, B, C) corresponding to c) is registered in the register 21.
Can be read from.

Although the counter in the above description was updated by incrementing by 1, the same effect can be obtained by giving the distance between records by a negative number even if it is decrementing by 1. It is not intended to limit the scope of the invention.

〔The invention's effect〕

According to the present invention, there is an effect that it is possible to easily achieve high speed search processing of a data string of a specific field in a structured relational database in a record format.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
3 is a block diagram of an embodiment of a comparison means used in the figure, FIG.
The figure is a diagram for explaining the names of each part of the relational database structured in a table format. 1, 3, 5, 7 ... Counter, 2,6,21,23 ... Register, 9 ... Mode register, 4 ... Adder, 8 ...
Data string comparison means, 10 ... Gate circuit, 11 ... Control circuit, 22 ... Comparator.

Claims (1)

[Claims] 1. A first counter, a first register, in which first setting data is set in synchronization with a first end signal and which changes in units of number in synchronization with a data read signal, a first register, and an output of the first counter. A first adder that outputs the first setting data by adding the value of the first register to a value, a second counter that changes by a unit number in synchronization with a data write signal, a second register, and a data read signal And a third counter that generates the first end signal and returns to the initial state when the set value of the second register is finished, and the second counter when the first end signal is counted and the predetermined value is finished. A fourth counter for generating an end signal, a data string comparing means for comparing a series of read data strings with a registered data string, a gate circuit for selecting an output of the data string comparing means, and a gate Third register that specifies the operation of the circuit When the first has the DMA processing function
A control for outputting a data read signal with the content of the counter as a read address and outputting a data write signal with the content of the second counter as a write address when the output signal of the gate circuit is generated to write the content of the fourth counter. A direct memory access control device comprising a circuit.