JPH0833812B2 - Sorting device - Google Patents

Description

The present invention relates to a sort processing device, and more particularly to a sort processing device capable of executing sort processing at high speed by pipeline processing.

[Conventional technology]

Conventionally, the sorting process is performed by software, which requires the execution of many instructions. The sort process is a process of rearranging given data in a fixed order, that is, in ascending or descending order. For example, in the case of data consisting only of numbers or data consisting of English characters, there is an operation of arranging in order of magnitude.

In the computer, the alphabet is ASCII code or EBCDIC
Like the code, since the numbers are processed as numbers that maintain the order relation of magnitude, the ascending and descending sorting processes result in the magnitude relation of numbers.

Bubble sorting is one of the sorting methods by software. In bubble sort, a given data string is compared with the next data in order from the first data, and a series of operations for performing replacement as needed is repeated several times to perform sorting.

Table 1 is an example of a sorted data string
Four data strings from D0 to data D3 are shown. One data format consists of a key part having comparison values for sorting in the first half and a pointer part showing the actual record storage location in the second half. The data strings are sorted according to the key value of the key part, and the sorted records can be taken out by sequentially taking out the records indicated by the pointer part in the order of the sorting result.

The record length that is generally used can range from several bytes to several hundred bytes or more. By holding the storage location in the pointer part in this way, sorting can be performed without moving the actual record itself. You can

Now, consider a case where the data strings in Table 1 are sorted in ascending order by bubble sorting according to the key value. Key K0 to Key K3
The value of is 4,2,3,1 in order, and it is sorted in ascending order of 1,2,3,4. The state of the processing will be sequentially described with reference to FIG.

(1) First, the first and second key values, that is, key K0 and key
Read the contents of K1 and compare. If they are in ascending order, leave them as they are, and if they are not in ascending order, replace both.

(2) Next, read the second and third key values of the rearranged data string of (1), that is, the contents of the keys K0 and K2,
The same process as (1) is performed.

(3) Similarly, the same processing as (1) is performed on the keys K0 and K3. The comparison and rearrangement operations up to the final data are completed, and the key K0 having the largest key value is moved to the end of the column.

(4) Next, the three keys remaining from the beginning, namely key K1,
Similar comparison and rearrangement processing is performed again on the keys K2 and K3. First, the first and second keys K1 and key
K2 processing is performed. In this case, the keys K1 and K2 have already been arranged in ascending order, so that the keys are not rearranged and remain as they are.

(5) Next, the second and third keys K2 and K3 are processed. As described above, the second comparison and rearrangement operation is completed, and the key K2 having the second largest key value is moved to the end of the three keys for which the comparison operation is performed.

(6) Similar comparison and rearrangement processing is performed on the two keys remaining from the beginning, that is, the keys K1 and K3.

As described above, the ascending sort according to the key value is completed by the series of operations (1) to (6), and the records indicated by the pointers are taken out in this order to obtain the record array after the ascending sort.

The number of comparison operations in the operations (1) to (6) is 3
+ 2 + 1 = 6 times, and in general, the maximum number of comparison operations of n data arrays is (n-1) + (n-2) + ... +
1 = n (n-1) / 2 times. Furthermore, in the conventional software processing, one comparison operation is performed by (1) a key address generation instruction, (2) a key load instruction, (3) a key comparison instruction, and (4) a branch to a processing routine depending on the comparison result. Instruction (5) Store instruction for data exchange (6) Update instruction for remaining data number (7) Branch instruction for repetition It was executed by a large number of instructions.

[Problems to be Solved by the Invention]

The conventional software sort process described above requires the execution of a large number of instructions, and most of the processes are executed sequentially depending on the result of the previous instruction, so that the processing time is extremely long. There are drawbacks.

[Means for solving the problem]

A first sort processing device according to the present invention comprises: a first and a second data buffer; and one of the first and second data buffers as a read buffer for data to be sorted,
A means for selecting the other as the save buffer for the data to be sorted, a means for inputting the data to be sorted given from the outside to the data buffer selected for reading the data to be sorted first, and the data for the sort First and second resists for holding the output of the reading buffer of, the means for sequentially storing the data to be sorted in the first and second registers, and the first and second registers for sorting. Each time data is stored, the contents of the predetermined parts of the first and second registers are compared with each other, and the comparing means outputs the comparison result; and the comparing means saves the value of the first register. If it is output that the data should be saved, the data held in the first register is saved in the save buffer, and the data held in the second register is If the comparison means outputs the fact that the value of the second register should be saved, the new data is stored in the first register and the next comparison operation is executed. The data held in the second register is saved in the save buffer, the data held in the first register is held as it is, the new data is stored in the second register, and the next operation is executed. When the comparing means and the saving means for all the data designated in advance are completed, the data held in one of the first and second registers without being saved in the save buffer. To a storage location designated in advance, and the data buffer used as the save buffer as a read buffer for the data to be sorted, and the other for the data to be sorted. Re-selected as the 避用 buffer,
It has means for reading data to be sequentially sorted from the reselected read buffer, and repeating the series of comparison operations, save operation to the save buffer, and output operation of result data.

The second sort processing device of the present invention includes a first register and a second register, and the first register and the second register each time data to be sorted is stored in the first register and the second register. Comparing the contents of the predetermined parts of each other and outputting the comparison result, and according to the comparison result of this comparing means, store the new data to be sorted in either the first register or the second register. Register specifying means for specifying a key, means for storing new data to be sorted in one of the first and second registers according to the specification of the register specifying means, and all data to be sorted by the register specifying means And a detection means for detecting whether the first and second registers are alternately designated, and if there is a detection output of this detection means, all the data to be sorted is There has been and means output to terminate the sorting process in accordance with the detection, defined all data to be the sort previously sequence that is already sorted data.

[Action]

Since both the first and second sort processing devices perform the sort processing by pipeline processing by hardware, the processing time becomes short and the processing speed is increased.

It should be noted that the first sort processing device has a drawback that the subsequent wasteful process is executed even when the sort process is completed while the bubble sort is being executed. The second sort processing device reduces unnecessary execution of sort processing by detecting whether or not the sort processing has already been completed during execution of bubble sort, thereby further speeding up sort processing. Is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of the system configuration including the sorting apparatus of the present invention.

The main storage device 1 is a storage device for storing instruction words and operands, and the buffer storage control device 2 reads the instruction words and operands from the main storage device 1 and sends them to the request source according to the instruction of the request source. , A storage controller for storing the calculation result in a predetermined location, a calculation controller 3 for executing a predetermined calculation in accordance with an instruction from the instruction controller 4, and a command controller 4 for reading a command word from the main memory 1. An instruction control device for decoding and instructing the operation control device 3 or the sort processing device 5 to execute an operation, a sort processing device 5
Is a sort processing device of the present invention.

The system configuration of this embodiment is such that the sort processing device 5 of the present invention is added to a known system configuration including a main storage device 1, a buffer storage control device 2, an operation control device 3, and an instruction control device 4. There is. The sorting device 5
May be built in the arithmetic and control unit 3.

The instruction word read from the main storage device 1 by the buffer storage control device 2 is decoded by the instruction control device 4, and when it is a sort instruction, it is notified to the sort processing device 5.

The sort command has information indicating the storage location of the data to be sorted and the storage location of the sorted data, and further has a field indicating the number of data to be sorted and whether to sort in ascending order or descending order. Have Both the storage location of the data to be sorted and the storage location of the sorted data are stored in the memory in the main storage device 1. As shown in Table 1, the sort data of this embodiment is composed of a key portion and a pointer portion, and is 8-byte fixed length data of 4 bytes for the key portion and 4 bytes for the pointer portion, which are continuously arranged on the memory. When executing the sort processing, the instruction control device 4 may control the request for reading the data to be sorted and the request for storing the sorted data, or the sort processing device 5 itself may control the request. In this embodiment, the instruction control unit 4 controls the control, sequentially reads out the data to be sorted which are continuously arranged in the memory, and sends the data to the sort processing unit 5. The instruction control device 4 also notifies the sort processing device 5 of the number of pieces of data to be sorted and an instruction as to whether to sort in ascending order or descending order.

FIG. 1 is a block configuration diagram of a first embodiment of a sort processing device 5 of the present invention.

SL10 is a register for holding the number of data to be sorted or the output of the counter 50 sent from the instruction control unit 4, the counter 50 is a subtractor for subtracting the content of SL10 by -1, and the selector 30 is sent from the instruction control unit 4. A selector that selects and outputs one of the number of data to be sorted and the output of the counter 50, SDB20 and SDB21 are buffers that store the data to be sorted, and WAR11 and WAR13 are the write addresses of SDB20 and SDB21. Write address registers, RAR12 and RAR14 are read address registers and counters that hold the read addresses of SDB20 and SDB21.
51 to 54 are adders that add +1 to the contents of WAR11, RAR12, WAR13, and RAR14, selectors 31 to 34 are selectors that select the reset value 0 and the outputs of counters 51 to 54, and SDR16 and SDR17 are from SDB20 or SDB21. The registers that hold the read data to be sorted, selectors 36 and 37,
A selector for selecting the data to be sorted read from SDB20 or SDB21, SDR18 receives the result data output from SDR16 or SDR17, and stores the result data in the main storage device 1.
The interface register that sends the result data to the buffer storage controller 2 for storing in the
The selector 40, which selects the output data of R16 and SDR17, is the data to be sorted which is read from the main memory 1 and sent to the sort processing device 5, or SDR16 and SDR.
Selector to select one of the output data from DR17, selector 41 to select the output data from SDR16 and SDR17, FGR15 to specify one of SDB20 and SDB21 as a read buffer for data to be sorted Then
A flag register that designates the other as a buffer for saving the data to be sorted, a selector 35 that selects an initial value 0 and a value obtained by inverting the contents of the FGR 15, and a comparator 23
Is a predetermined part of the data to be sorted held in SDR16 and SDR17, that is, in this embodiment, the contents of the key part of the data to be sorted are compared with each other, and a comparator and comparator 22 for outputting the comparison result Is the contents of SL10 and RAR12 or RAR14
Of the RAR12 and RAR14, a selector 39 for selecting the contents of RAR12 and RAR14, and a control circuit 24 for controlling the entire sort processing device 5. is there.

Next, the operation of sorting the data strings in Table 1 by the sort processing device 5 of this embodiment will be described.

Now, consider a case where the data sequence of Table 1, that is, four data of data D0 to data D3 are continuously arranged in the memory, and this data sequence is sorted in ascending order. Data D0 in Table 1
The data D3 are sequentially read from the main storage device 1 by the buffer storage control device 2 and sent to the sort processing device 5. Further, the number “4” of data to be sorted indicated by the sort command is decoded by the command control device 4 and sent to the sort processing device 5.

FIG. 2 is a timing chart showing an operation of sorting the data strings, data D0 to data D3, in Table 1 by the sort processing device 5.

In the cycle T0, SL10, WAR11, RAR12, WAR13, and RAR14 maintain the initial value 0. Further, the sort length, that is, the number “4” of data to be sorted is sent from the instruction control device 4 to the sort processing device 5,
Set to SL10 in cycle T1. At the same time, the initial value "0" is set in FGR15. When the FGR15 holds the value "0", it is instructed to use the SDB20 as a read buffer for the data to be sorted and the SDB21 as a save buffer for the data to be sorted. On the other hand, FGR15
Is set to the value "1", it is instructed to use SDB20 as a buffer for saving data to be sorted and SDB21 as a buffer for reading data to be sorted.

In the cycles T1 to T4, the data D0 to D3 read from the main storage device 1 to be sorted are sequentially sorted by the sort processing device 5.
Are transferred to SDB20, the write address register WAR11 of SDB20 is sequentially incremented, and SDB2 is incremented during cycles T2 to T5.
Captured at 0. When the sort data D0 to D3 are taken into the SDB20, the data are sequentially read out to the SDR16 and SDR17, and the comparator 23 compares the key parts of the data. First, in cycle T3, sort data D0 read from word 0 of SDB20 is set in SDR16, and in cycle T4 sort data D1 read from word 1 of SDB20 is set in SDR17. When the data is stored in SDR16 and SDR17, the comparator 23 compares the keys, and the control circuit 24 is notified of the comparison result. Comparator 23 is composed of a function to detect the magnitude of SDR16 and SDR17 and a function to detect a match. When SDR16 <SDR17, a logic “1” is output, and when SDR16> SDR17, a logic “0” is output, and SDR16 When = SDR17 is detected, a coincidence signal is notified to the control circuit 24 in addition to the above signal.

In cycle T4, the key parts of the sort data D0 in SDR16 and the sort data D1 in SDR17 are compared, the comparator 23 outputs a logic "0", and notifies the control circuit 24.

In this embodiment, since the ascending sort is performed by the bubble sort, the sort data having a larger key value is used for comparison with the next sort data, and the sort data having a smaller key value is stored in the save buffer. Are evacuated to. By the save operation to the save buffer, the sort data replacement process in the bubble sort is executed.

In cycle T5, the sort data D1 in SDR17 is saved in word 0 of SDB21 designated as a save buffer for the data to be sorted by the control of the control circuit 24 which receives the output result of the logic "0" from the comparator 23. And at the same time SDB20
Sort data D2 read for the next comparison operation from word 2 of is set in SDR17. The comparison operation is performed again by the comparator 23, and the sort data D2 having a smaller key value is displayed.
Are saved to word 1 of SDB21 in cycle T6. In cycle T6, the last sort data D3 read from word 3 of SDB20 is set in SDR17. By the comparison operation of the comparator 23 in the cycle T6, the sort data D3 having a smaller key value is saved in the word 2 of the SDB21 in the cycle T7.

SDB20, SDB21 write address registers WAR11, WAR13
The read address registers RAR12 and RAR14 are incremented by +1 each time a write or read operation is performed to indicate the next address. Therefore, the last sort data D3 from word 3 of SDB20 is read in cycle T5, set in SDR17 in cycle T6, and at the same time RAR12 is counted up to indicate word 4 of SDB20. The selector 39 selects the content of the read address register on the side used as a read buffer for the data to be sorted and outputs it to the comparator 22, which compares it with the content of SL10. cycle
At T6, the content of RAR12 is "4", which matches the content of SL10 "4". The comparator 22 outputs a coincidence signal and notifies the control circuit 24. This coincidence signal indicates that all sort data comparison operations in the read buffer for the data to be sorted have been completed. Control circuit receiving this comparison operation end signal
By the control of 24, the following operation is performed in cycle T7.

First, according to the result of the comparison operation of the comparator 23, the sort data D3 in the SDR 17 having a small key value is stored in the save buffer S.
Sort data D0 having the maximum key value remaining in SDR16 and saved in word 3 of DB21 is set in SDR18,
Sent to the buffer storage controller 2 for storage in a predetermined location in memory.

SL10 is updated to the value "3" subtracted by the subtractor 50. This value indicates the remaining number of data to be sorted which is held in the sort processing device 5.

The value of each address register of WAR11, RAR12, WAR13, and RAR14 is reset to the initial value "0".

Further, the FGR 15 is updated to a value in which its contents are inverted, that is, the value “1”. This indicates that after the cycle T7, the SDB20 is used as a save buffer for data to be sorted and the SDB21 is used as a read buffer for data to be sorted, and the series of processing operations described above are repeated according to this instruction. .

That is, in cycles T8 to T10, the sort data held in word 0 to word 2 of SDB21 is SDR16 or SDR.
The data is sequentially read by 17, and the comparison operation is performed by the comparator 23, and the sort data having a small key value is sequentially saved from the word 0 of the SDB 20 according to the instruction of the FGR 15.

In cycle T10, the match between the value of RAR14 and the value of SL10 is detected, and the control circuit 24 is notified of the end of the comparison operation. Then, in cycle T11, the sort data D3 having the small key value held in SDR16 is saved in word 1 of SDB20, and at the same time, the sort data D2 having the largest key value in the remaining sort data is changed from SDR17 to SDR18. It is set and sent to the buffer storage controller 2. Also, in cycle T11, the value of SL10 changes from “3” to “2” and the value of FGR15 changes from “1” to →
It is updated to "0", the value of each address register of WAR11, RAR12, WAR13, RAR14 is reset to the initial value "0", and a new comparison operation and save operation are executed.

In cycle T13, the remaining two sort data D1 and D3
Is performed, the sort data D3 having a small key value is saved in the word 0 of the SDB21 in the cycle T14, the sort data D1 having a large key value is set in the SDR18, and is stored in the buffer storage controller 2. Sent out.

In cycle T15, the last sort data D3 read from word 0 of SDB21 is set in SDR16. At this time, SDB21
The read address register RAR of has been counted up to the value "1", selected by the selector 39 and SL by the comparator 22.
It is compared with the value “1” of 10 and the coincidence signal is notified to the control circuit 24. Since valid data is not set in SDR17, the control circuit 24 sets the last sort data D3 held in SDR16 in cycle T16 in SDR18 and sends it to the buffer storage controller 2. In cycle T16, S
The value indicating the remaining sort data of L10 becomes “0”, and the completion of all sort processing operations causes the control circuit 24 through the comparator 22.
Is notified, and a series of sort processing operations ends.

The result of the ascending sort is obtained by retrieving the pointer portion of the sort data in a reverse order of the store order from a predetermined location in the memory where the sort data is stored.

The descending sort can be performed in the same manner as the ascending sort.

Next, a processing procedure when the data string of Table 2 is sorted in ascending order by bubble sorting by the sorting apparatus according to the key value will be briefly described with reference to FIG.

The values of keys K0 to K3 are 4,1,2,3 in order, and they are rearranged in ascending order of 1,2,3,4.

(1) First, the first and second key values, that is, key K0 and key
Read the contents of K1 and compare. If they are in ascending order, leave them as they are, and if they are not in ascending order, replace both.

(2) Next, read the second and third key values of the rearranged data string of (1), that is, the contents of the keys K0 and K2,
The same process as (1) is performed.

(3) Similarly, the same processing as (1) is performed on the keys K0 and K3. The comparison and rearrangement operations up to the final data are completed, and the key K0 having the largest key value is moved to the end of the column.

(4) Next, the three keys remaining from the beginning again, that is, the keys
Similar comparison and rearrangement processing is performed on K1, key K2, and key K3. First, the first and second keys K1 and key
K2 processing is performed. In this case, the keys K1 and K2 have already been arranged in ascending order, so that the keys are not rearranged and remain as they are.

(5) Next, the second and third keys K2 and K3 are processed. As described above, the second comparison and rearrangement operation is completed, and the key K3 having the second largest key value is moved to the end of the three keys for which the comparison operation is performed.

(6) The same comparison and rearrangement processing is performed on the two keys remaining from the beginning, that is, the keys K1 and K2.

As described above, the ascending sort according to the key value is completed by the series of operations (1) to (6), and the records indicated by the pointers are taken out in this order to obtain the record array after the ascending sort.

The number of comparison operations in the operations (1) to (6) is 3
+ 2 + 1 = 6 times.

As described above, since the sorting apparatus of FIG. 1 described above uses the bubble sorting algorithm as it is in hardware, as in the case of sorting the data strings of Table 2 in ascending order, the sorting apparatus of FIG. Processing procedure (1)-
Even when the sort process is completed by the process up to (3), the subsequent processes (4) to (6) are automatically executed, that is, the sort process is performed during the bubble sort. Even when is completed, the subsequent useless processing is executed, and there is a drawback that speeding up is hindered.

Next, a second embodiment of the present invention which solves the drawbacks of the first embodiment will be described with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of a system configuration including the sort processing device of the present invention.

The main storage device 1 is a storage device for storing instruction words and operands, and the buffer storage control device 2 reads the instruction words and operands from the main storage device 1 and sends them to the request source according to the instruction of the request source. , A storage controller for storing the calculation result in a predetermined location, a calculation controller 3 for executing a predetermined calculation in accordance with an instruction from the instruction controller 4, and a command controller 4 for reading a command word from the main memory 1. An instruction control device for decoding and instructing the operation control device 3 or the sort processing device 5 to execute an operation, a sort processing device 5
Is a sort processing device of the present invention.

The system configuration of the present embodiment is a configuration in which the sort processing device 5 of the present invention is added to a known system configuration including a main storage device 1, a buffer storage control device 2, an arithmetic control device 3, and an instruction control device 4. There is. Also, the sort processing device 5
May be built in the arithmetic and control unit 3.

The instruction word read from the main storage device 1 by the buffer storage control device 2 is decoded by the instruction control device 4, and when it is a sort instruction, it is notified to the sort processing device 5.

The sort command has information indicating the storage location of the data to be sorted and the storage location of the sorted data, and further has a field indicating the number of data to be sorted and whether to sort in ascending order or descending order. Have Both the storage location of the data to be sorted and the storage location of the sorted data are stored in the memory in the main storage device 1. As shown in Table 2, the sort data in the present embodiment is composed of a key portion and a pointer portion, and is 8 bytes fixed length data of 4 bytes for the key portion and 4 bytes for the pointer portion, which are continuously arranged in the memory. When executing the sort processing, the instruction control device 4 may control the request for reading the data to be sorted and the request for storing the sorted data, or the sort processing device 5 itself may control the request. In this embodiment, the instruction control unit 4 controls the control, sequentially reads out the data to be sorted which are continuously arranged in the memory, and sends the data to the sort processing unit 5. The instruction control device 4 also notifies the sort processing device 5 of the number of pieces of data to be sorted and an instruction as to whether to sort in ascending order or descending order.

FIG. 3 is a block diagram of the second embodiment of the sort processing device 5 of the present invention.

SL10 holds the number of pieces of data to be sorted sent from the instruction control unit 4, and the register showing the number of pieces of data to be sorted held in the sort processing unit 5, the counter 50 sets the content of SL10 to -1. The selector 30, selector 30 is a selector for selecting and outputting either the number of data to be sorted sent from the instruction control unit 4 or the output of the counter 50 and the initial value "0", and SDB20 and SDB21 are sorts. Buffers, WAR11 and WAR13, that hold the data that should be
Is a write address register that holds the write address of SDB20 and SDB21, RAR12 and RAR14 is a read address register that holds the read address of SDB20 and SDB21, and counters 51 to 54 are WAR11, RAR12, WAR13, RAR14
The counters 55 and 56 are RAR
Subtractor and selector 3 for subtracting -1 from the contents of 12 and RAR14 respectively
Selectors 1 and 33 select the reset value 0 and the outputs of the counters 51 and 53 respectively. Selectors 32 and 33 select the reset value 0 and the contents of the counters 52 and 55, 54 and 56 and WAR 11 and WAR 13, respectively. SDR16 and SDR17 are registers for holding the data to be sorted read from SDB20 or SDB21, selectors 36 and 37 are selectors for selecting the data to be sorted read from SDB20 or SDB21, SD
R18 is an interface register that receives the result data output from SDR16 or SDR17 and sends the result data to the buffer storage control device 2 in order to store the result data in the main storage device 1. The selector 38 is the SDR16 and SDR17.
Selector 40 for selecting the output data from the main memory device 1 and the selector 40 for selecting either the data to be sorted which is read out from the main storage device 1 and sent to the sort processing device 5 or the output data from the SDR16 and SDR17. , Selector 41 is SD
Selector to select output data from R16 and SDR17, FG
R15 is a flag register that designates one of SDB20 and SDB21 as a read buffer for data to be sorted and the other as a save buffer for data to be sorted, and the selector 35 has the contents of FGR15 with an initial value of 0. The selector, which selects the value subjected to the inversion, the comparator 23 is a predetermined part of the data to be sorted held in the SDR16 and SDR17, that is, the contents of the key part of the data to be sorted in this embodiment. Comparator for comparing and outputting the comparison result,
The comparator 22 compares the content of SL10 with the content of either RAR12 or RAR14, detects a match and outputs the comparator, the selector 39 selects the content of RAR12 and RAR14, and the gate circuit 25. Is an inverter that inverts the contents of the comparator 23, the register 19 is an initial value "0" or "1" or a register that holds the output of the comparator 23, and the selector 42 is an initial value "0" or "1" and a comparator Selector for selecting 23 outputs, comparator 26
Is a comparator that compares the output of the gate circuit 25 with the output of the register 19 to detect a match, and the control circuit 24 is a control circuit that controls the entire sort processing device 5.

Next, the operation of sorting the data strings in Table 2 by the sort processing device 5 of this embodiment will be described.

Now, consider a case where the data string in Table 2, that is, the four data D0 to D3 are continuously arranged in the memory, and this data string is sorted in ascending order. Data D0 in Table 2
The data D3 are sequentially read from the main storage device 1 by the buffer storage control device 2 and sent to the sort processing device 5. Further, the number of data to be sorted “4” indicated by the sort instruction is decoded by the instruction control device 4,
It is sent to the sort processing device 5.

FIG. 4 is a timing chart showing the operation of sorting the data strings, data D0 to data D3 in Table 2, by the sort processing device 5.

SL10, WAR11, RAR12, WAR13, RAR14 in cycle T0
Keeps the initial value 0 reset. Also,
The sort length, that is, the number "4" of data to be sorted is sent from the instruction control unit 4 to the sort processing unit 5 and set in SL10 in cycle T1. At the same time, the initial value "0" is set in FGR15. When FGR15 holds the value "0", it instructs to use SDB20 as a read buffer for data to be sorted and SDB21 as a save buffer for data to be sorted. On the other hand, FG
When R15 is set to the value "1", it is instructed that SDB20 be used as a save buffer for data to be sorted and SDB21 be used as a read buffer for data to be sorted.

In the cycles T1 to T4, the data D0 to D3 to be sorted read out from the memory are sequentially transferred to the sort processing device 5, the write address register WAR11 of the SDB20 is sequentially counted up, and the cycles S2 to T5 are repeated. Is taken into. When the sort data D0 to D3 are taken into the SDB20, the data are sequentially read out to SDR16 and SDR17, and the comparator
At 23, a comparison of the key parts of the data is made. Register 19
Is reset to an initial value "0" when performing ascending sort, to an initial value "1" when performing descending sort, and to "0" in this case. First, SD in cycle T3
Sort data D0 read from word 0 of B20 is set in SDR16, and sort data D1 read from word 1 of SDB20 is set in SDR17 in cycle T4. SDR16 and SD
When the data is stored in R17, the comparator 23 compares the key parts, and the comparison result is notified to the control circuit 24. The comparator 23
It is composed of the function to detect the size of SDR16 and SDR17 and the function to detect the match. When SDR16 <SDR17, the logic is "1".
When SDR16> SDR17, a logic "0" is output, and SDR16 = SDR
When 17 is detected, a coincidence signal is notified to the control circuit 24 in addition to the above signals.

In cycle T4, the key parts of the sort data D0 in SDR16 and the sort data D1 in SDR17 are compared, the comparator 23 outputs a logic "0", and notifies the control circuit 24. At this time, the comparator 26 compares the value "1" of the contents of the comparator 23, which has been inverted by the gate circuit 25, with the value "0" held in the register 19, and simultaneously the logic "0" indicating the disagreement is obtained. The control circuit 24 is notified. This means that the sort data D0 held in the SDR16 and the sort data D1 held in the SDR17 are not arranged in ascending order, and a sort data replacement process is necessary. In other words, the top sort data is SD
The data is stored in R16, the second sort data is stored in SDR17, and the comparison operation is executed. If the first data D0 and the second data D1 are already sorted in ascending order,
The comparator 23 outputs the logic "1" because the second data holds the larger key value, and the value "0" inverted by the gate circuit 25 is the initial value "0" of the register 19. Should be compared to find a match. In ascending sort by bubble sort, sort data having a larger key value is used for comparison with the next sort data, and sort data having a smaller key value is replaced with the next new sort data. Therefore, if all sort data are already sorted in ascending order, the sort data will be
It should be input to SDR16 and SDR17 alternately like SDR16 → SDR17 → SDR16. That is, the output of the comparator 23 is also "1".
→ "0" → "1" should be repeated alternately. That is, the value of the register 19 is updated each time by the output value of the comparator 23, holds the previous comparison result, is compared with the current comparison result, and detects whether or not the sort data is arranged in ascending order. .

If the key value of the sort data supplied for the new comparison operation is equal to the key value of the sort data left for the previous comparison operation, the register holding the previous sort data is used. And the contents of the register 19 are held as they are without being updated, and until the new sort data having a different key value is supplied to the register holding the new sort data, the register holding the new sort data is Contents are updated.

It should be noted that when the descending sort is performed, the initial value of the register 19 is reset to "1", and the same applies thereafter.

Again, returning to FIGS. 3 and 4, the continuation of the operation of this embodiment will be described.

In the present embodiment, the sort data having a larger key value is used for comparison with the next sort data, and is therefore held in the register as it is, and the sort data having a smaller key value is saved in the save buffer. By this save operation to the save buffer, the sort replacement processing in the bubble sort is executed.

In cycle T5, the sort data D1 in SDR17 is saved in word 0 of SDB21 designated as a save buffer for the data to be sorted by the control of the control circuit 24 which receives the output result of the logic "0" from the comparator 23. And at the same time SDB20
Sort data D2 read for the next comparison operation from word 2 of is set in SDR17. The comparison operation is performed again by the comparator 23, and the sort data D2 having a smaller key value is displayed.
Are saved to word 1 of SDB21 in cycle T6. In cycle T6, the last sort data D3 read from word 3 of SDB20 is set in SDR17. By the comparison operation of the comparator 23 in the cycle T6, the sort data D3 having a smaller key value is saved in the word 2 of the SDB21 in the cycle T7.

SDB20, SDB21 write address registers WAR11, WAR13
The read address registers RAR12 and RAR14 are incremented by +1 each time a write or read operation is performed to indicate the next address. Therefore, the last sort data D3 from word 3 of SDB20 is read in cycle T5, set in SDR17 in cycle T6, and at the same time RAR12 is counted up to indicate word 4 of SDB20. The selector 39 selects the content of the read address register on the side used as a read buffer for the data to be sorted and outputs it to the comparator 22, which compares it with the content of SL10. cycle
At T6, the content of RAR12 is "4", which matches the content of SL10 "4". The comparator 22 outputs a coincidence signal and notifies the control circuit 24. This coincidence signal indicates that all sort data comparison operations in the read buffer for the data to be sorted have been completed. In addition, since the series of sort data is not already sorted in ascending order, the cycle is controlled by the control circuit 24 which receives this comparison operation end signal.
The following operations are performed at T7.

First, according to the result of the comparison operation of the comparator 23, the sort data D3 in the SDR 17 having a small key value is stored in the save buffer S.
Sort data D0 having the maximum key value remaining in SDR16 and saved in word 3 of DB21 is set in SDR18,
Sent to the buffer storage controller 2 for storage in a predetermined location in memory.

SL10 is updated to the value "3" subtracted by the subtractor 50. This value indicates the remaining number of data to be sorted which is held in the sort processing device 5.

The value of each address register of WAR11, RAR12, WAR13, and RAR14 is reset to the initial value "0", and the register 19 is also reset to the initial value "0". Further, the FGR 15 is updated to a value in which its contents are inverted, that is, the value “1”. This indicates that after the cycle T7, the SDB20 is used as a save buffer for data to be sorted and the SDB21 is used as a read buffer for data to be sorted. The operation up to this point is the same as that of the sort processing apparatus in FIG. 1, and the series of processing operations described above are repeated in accordance with this instruction.

That is, in cycles T8 to T10, the sort data held in the word 0 to the word 2 of the SDB21 are sequentially read by the SDR16 or SDR17, and the comparison operation is performed by the comparator 23, so that the sort data having a small key value is FGR15. SDB20
Are sequentially saved from the word 0. By the way, in the series of comparison operations this time, the comparator 26 outputs a logic "1" in which all sort data are sorted in ascending order, and it is detected that all sort data are already sorted in ascending order, and the control circuit 24 To notify. At the same time, in cycle T10, a match between the value of RAR14 and the value of SL10 is detected, and the control circuit 24 is notified of the end of the comparison operation.After that, since all sort data have already been sorted in ascending order, Termination processing is executed.

First, in cycle T11, sort data D2 having a small key value held in SDR17 is saved to word 1 of SDB20, and at the same time sort data D3 having the largest key value among the remaining sort data is changed from SDR16 to SDR18. It is set and sent to the buffer storage controller 2. Also, cycle T11
Then, the value of SL10 is reset to the value "0" which indicates the number of remaining sort data, and the pointer value of WAR11 held in cycle T10 to sweep out the sorted data sorted in ascending order saved in SDB20 is cycled. Moved to RAR12 at T11. Then, the pointer value of RAR12 is decremented by -1, and sort data D2 and D1 are obtained from words 1 and 0 of SDB20.
Is read out, set in SDR16 in cycles T12, T13, subsequently set in SDR18 in cycles T13, T14, and sent to the buffer storage control device 2 to complete the entire sort processing operation.

The result of the ascending sort is obtained by retrieving the pointer portion of the sort data in a reverse order of the store order from a predetermined location in the memory where the sort data is stored.

The descending sort can be performed in the same manner as the ascending sort.

〔The invention's effect〕

As described above, the present invention has the effect that it can be executed at high speed by performing the sorting process, which has been conventionally executed sequentially by a large number of software instructions, by the pipeline process by hardware, and the execution of bubble sort By detecting whether or not the sorting process has already been completed, there is an effect that unnecessary execution of the sorting process is reduced and the sorting process can be further speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a sort processing apparatus of the present invention, FIG. 2 is a timing chart showing an operation of sort processing executed by the sort processing apparatus of FIG. 1, and FIG. 2 is a block diagram of a second embodiment of the sort processing apparatus, FIG. 4 is a timing chart showing the operation of the sort processing executed by the sort processing apparatus of the present embodiment, and FIG. 5 is the entire system including the sort processing apparatus. FIG. 6 and FIG. 7 are diagrams showing the operation of a sort process by bubble sort according to an embodiment of the present invention. 1 ... Main storage device, 2 ... Buffer storage control device, 3 ...
... arithmetic control device, 4 ... command control device, 5 ... sort control device, 10 ... sort length register (SL), 11, 13
...... Write address register (WAR), 12,14 ...... Read address register (RAR), 15 …… Flag register (FG
R), 16, 17, 18 ... Sort data register (SDR), 19 ...
… Register, 20,21 …… Sort data buffer (SDB),
22,23,26 …… Comparator, 24 …… Control circuit, 25 …… Gate circuit, 30 to 42 …… Selector, 50,55,56 …… -1 Subtractor, 51
~ 54 …… + 1 adder.

Claims (2)

[Claims] 1. A first and second data buffer, and one of these first and second data buffers is a read buffer for data to be sorted, and the other is a save buffer for data to be sorted. A means for selecting as a buffer, a means for inputting data to be sorted externally given to the data buffer selected for reading the data to be sorted first, and holding the output of the buffer for reading the data to be sorted First and second registers, means for sequentially storing the data to be sorted in the first and second registers, and each time the data to be sorted is stored in the first and second registers A comparing means for comparing the contents of predetermined portions of the first and second registers with each other and outputting a comparison result, and this comparing means is a first register. When it is output that the value of the data should be saved, the data held in the first register is saved in the save buffer, the data held in the second register is held as is, and a new When the data is stored in the first register and the next comparison operation is executed, while the comparison means outputs that the value of the second register should be saved, it is similarly held in the second register. Existing data is saved in the save buffer, the data held in the first register is held as it is, the new data is stored in the second register, and the next operation is executed. When the comparing means and the saving means for all the data are completed, the data held in one of the first and second registers without being saved in the save buffer is designated in advance. A means for outputting to the storage location, and the data buffer used as the save buffer as a read buffer for the data to be sorted, and the other is reselected as a save buffer for the data to be sorted, and the reselected read is performed. A sorting processing device comprising: means for reading data to be sequentially sorted from the data buffer, and repeating the series of comparison operations, saving operation to the saving buffer, and outputting result data. 2. A first and a second register and the contents of a predetermined portion of the first and the second register each time data to be sorted is stored in the first and the second register. Comparing means for comparing each other and outputting a comparison result, and the first and second comparing means according to the comparison result of the comparing means
Register designating means for designating in which of the registers the new data to be sorted is stored, and according to the designation of the register designating means, the new data to be sorted is stored in one of the first and second registers. Means for detecting whether or not the register designating means alternately designates the first and second registers for all the data to be sorted, and when there is a detection output of the detecting means, Sorting processing for detecting that all the data to be sorted are already sorted data, outputting all the data to be sorted according to a predetermined order, and terminating the sorting processing. apparatus.