JPS6054043A - Sort processor - Google Patents

Abstract

PURPOSE:To perform the processing in a high speed by constituting a sort processing into a private hardware which makes a pipeline processing possible. CONSTITUTION:Element data (b) inputted to an S1 register 13 of a sort circuit 8 and element data (a) set beforehand in an S2 register 15 are compared with each other by a comparator 16. If the comparison result is (a)>(b) in case of sorting in the ascending order, data (b) is sent to an S3 register 18, and data (a) is returend to the S2 register again, and data are transposed. If the comparison result is (a)<=(b), it is judged that data (a) and (b) are arranged in the ascending order, and data (b) is sent to the S2 register 15, and data (a) is fed to the S3 register 18, and the comparator 16 leaves always larger data in the S2 register 15 and transfers smaller data to the S3 register to feed it to a vector register VR3. Consequently, when four element data in a vector register VR0 are allowed to pass the sort circuit 8, element data having a maximum value is transmitted last and is stored in a rightmost stage 10-3 of a vector register VR3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sorting processor provided in a data processing device, and particularly to a high-speed sorting processor having a hardware configuration capable of pipeline processing.

[Technology background]

So-called sorting processing, which arranges multiple pieces of data in descending or ascending order, has conventionally been performed using software. There are several types of sorting methods; one example is
A neighbor exchange sorting method related to the present invention will be described.

Figure 1 is an example of sorted data, record 1
4 pieces of data in each of DATAI to 4
are sorted according to keys KEYI to 4 included in each data. In the illustrated example, each value of KEY 1 to 4 is 4.3.1.2
The data is sorted in ascending order and the data is rearranged in the order of 1.2.3.4.

For convenience of explanation, the content (value) of KEY”α〃
is expressed as [β]α. Therefore, in the case of the data group shown in FIG. 1, the keys are mark 1, depression 2, l:L13, I
214 ・■ First, KEYI and KEY2
Read the contents of , compare them, and if they are arranged in ascending order, leave them as they are, and if they are not arranged in ascending order, exchange them.

■ For KEY 1 and KEY 3, process in the same way as ■.

I8, (a) l　, l':'D8, (2).

2≦o, , [11,, (4) 5.1214 ■ Process in the same way as ■ for KEYl and KEY4.

■ The largest key value is transported to the right. Next, the remaining 3
Similarly, rearrange the @ keys in ascending order. First, K.
EY2 and EY3 are processed.

■ Process KEY2 and KEY4 in the same way.

(xis, ra+□, (2), 1 mark.

Dos, 045C3bl O+ ■ The second largest key value is moved to the right end.

Next, the remaining two keys are rearranged in ascending order in the same way. That is, KEY3 and EY4 are processed.

The note processing of Mountain 5, Agony, 1 (3) 2, (4) 1 is completed, and the ascending order of the 4 keys is 1]
D3, (2) 4, ■4, (4).

is obtained, and a sorted array of data or records is created according to the key number.

In the above sorting process, the number of comparisons is 3+2+1
= 6 times, and generally N(N-
1)/2 comparisons are required.

Furthermore, for one comparison, in a conventional general-purpose computer program, α, KEY address calculation instruction, KEY load instruction Cmi, comparison instruction dl, branching instruction g, K to select processing according to the comparison result.
There is a problem in that a large number of instructions are required, such as a load instruction f for FiY exchange and a branch instruction for repetition, and therefore a large amount of processing time is required.

In particular, in data processing for commercial purposes, etc., the weight of sorting processing is large, so there is a strong desire for faster processing.

[Object and structure of the invention]

An object of the present invention is to speed up the processing by converting the sorting process that was conventionally performed by software into dedicated hardware, and the configuration for this purpose is as follows:
means for sequentially inputting data in a data array to be sorted or data and its number into each of the first, second and third l/registers, and each time data is inputted into the first register; a comparison circuit that compares the contents of predetermined parts of the first register and the second register; If the data in the first register is moved to the second 17 register and the previous data in the second register is moved to the third register, while the second
In the case of a value of detecting whether an unsorted portion is included in the output data array obtained from the note circuit; and when it is detected that an unsorted portion is included; The present invention is characterized by comprising means for repeatedly inputting the output data array to the sorting circuit.

[Embodiments of the invention]

The details of the present invention will be explained below based on examples.

FIG. 2 is a configuration diagram of a system according to an embodiment of the present invention.

In the figure, 1 digit main memory, 2 buffer storage, 3 digit spacing register, 4 digit spacing operation unit, 5 channel, 6
indicates a vector register and a 7-digit sort processor.

1 to 5 are components of a conventional general-purpose computer, and elements 6 and 7 in the dotted line block are added parts according to the present invention. Furthermore, when added to a vector processing device, it is provided in parallel to a pipelined vector arithmetic unit.

FIG. 3 shows the structure of the sort command used in this embodiment. Although it is a 4-byte long instruction, the 4th byte is not used. OP is the instruction code section, R・1 is the output operand register number, R21d: input operand・l
/Represents register number.

FIG. 4 is a circuit diagram of one embodiment of the sorting processor. In the figure, 6 is a vector register, 7 is a sorting processor, 8 is a sorting circuit, and 9 is a sorting completion detection circuit.

Vector register 6 contains V B, OlV B, i
, V B, 2, 4 (fixed element vector register, input I/register 1, output register 12)
Consists of.

Vector registers V B, 0 to V El, 3
each consists of N stages and can store N1-specific element data or keys, but here, to simplify the explanation, in the case of N=4, four stages 10-
0.10-1.10-2.1o-3.

The sort processor 7 includes an S register 13, a selector 14, an S
21/Jister] 5, comparison circuit 16, selector 17, S3
It is composed of a register 18, an S4 register 19, a comparison circuit 20, and a flag latch 2J.

Next, the circuit operation will be described.

The sort instruction shown in FIG. 2 specifies all vector registers VFI and 0 as input operand disk R2,
It is assumed that the vector register VR.3 is specified as the output operand register (, 1).

This one sort instruction causes the four stages 10-
Four element data from 0 to 10-3 are read out in the 11th order and are supplied to the sorting processor 7 via the output register 12. The note processor 7 performs a sorting process in a square format, and sequentially outputs the four element data as a result of the processing. These element data are input to the input register 111F.
r: are sequentially written into the four stages 10-0 to 10-3 of the vector register V It 3 through the vector register V It 3 .

The sorting circuit 8 operates as follows.

The 9-element data "b" input to the S register 13 and the S2
The previous element data Nα in the register 15 is compared with the previous element data Nα in the comparison circuit 16. Selectors 14 and 17
is controlled by the comparison result of the comparison circuit 16. In addition,
Here, it is assumed that ascending order sorting is performed.

If the comparison result is α>b, it means that α and b are against the ascending order arrangement, so Nb in the S register 13
1l is sent to S3 register 18, and S2 register 15
XXα〃 inside is returned to the S2 register 15 again. That is, an exchange process for changing the order is performed. On the other hand,
If the comparison result is α less b, it means that α and b are arranged in ascending order, so %t in the S register 13
/, # ij Moved to 82 register 15 and placed in S2 register 15 i SSα77 Ha S3 register 18
Send in order to Rel.

In this way, the comparison circuit 16 compares the contents of the S register 13 and the 82 register 15, and always leaves the larger one in the 82 register 15, moves the smaller one to the S3 register, and sends it to the vector register VR3. . Therefore, when the four element data in the vector register VR.0 are passed to the note circuit 8, the element data with the largest value is sent out last. The element data with this maximum value is
It is stored in the rightmost stage 10-3 of vector register VR,3.

Then input operand register I(2 as V f(
, 3 and, for example, specify V (・0 as the output operand・
1/Execute the sort command to register R1.

Thereby, the second largest element data can be determined.

Next, specify VROe as the input operand register R2, and specify VROe as the output operand register R1.
Execute a sort command that specifies 3.

This allows the arrangement of the remaining two element data to be determined.

As described above, complete sorting processing is performed by repeatedly passing the four element data to be noted through the note circuit 8 three times. The end of sorting will be described later.

It is controlled using a sort completion detection circuit 9.

FIGS. 5(α), (b), and (c) show four element data to be noted, key marks 1, I!, used in the explanation of the conventional example. 1
2.0]3, ■4 An example of the operation of the sorting circuit is shown.

FIG. 5(a) shows the first sorting process, FIG. 5(b) shows the second sorting process, and FIG. 5(c) shows the contents of each register in the third sorting process S2 and S3. are doing.

In order to make the comparison circuit 16 function correctly for the first and last keys, a constant co- is set before the data, and a constant 69'' is set after the data by hardware.

In the first sorting process shown in FIG.
In the second sorting process shown in (b) of the same figure, the second largest key 2 is output from the 83rd register after the largest key mark, and in the third note processing shown in (c) of the same figure, So, 3
The largest key 1214 is key (4) 1, (:(1
After 2, it is output from register 83. In other words, sorting is completed in three processes.

Generally, in the case of sorting N keys, sorting is completed by repeating the sorting process N-1 times. However, Fig. 5 (b
), if part or all of the original keyboard layout is already in ascending order, N-1
Sorting is completed in less than 1 times (2 times in the example of FIG. 5).

The sort completion detection circuit 9 in FIG. 4 has a function of detecting the early completion of the Hiko sort as described above, and stopping the subsequent processing to shorten the processing time. This circuit consists of 83 registers 18 of sort circuit 8.
Detects whether all element data output from is arranged in ascending order.

The element data output from the S3 register 18 is sequentially sent to the S4
It is stored in register 19. The comparison circuit 20 compares the content 6C of the S4 register 19 with the element data 5 (dN) output from the 83rd register J8 in the next step,
If c'>cl, that is, if the array is not in ascending order, the flag latch 21 is reset. Flag latch 21
is set to the 'ON/I' state by initial setting at the beginning of the repetition, and remains ON unless reset by the comparator circuit 20.
maintain condition.

Therefore, whether or not an ascending order relationship has been established between all element data can be determined by checking the value of this flag latch 21, and based on this, it is possible to control whether or not to perform the next sorting process. can.

Iterative control of note processing can be performed by software or microprogram control. In the case of forced processing, such as selecting only the two largest keys, it is also possible to complete the sorting process twice.

In addition, in the above example, a note is made using element data or a key, and the result of the note is output as element data or a key. It is also easy to change it to do so.

For example, in the example shown in Figure 5, the key number arrangement is 3.4.2, ■
is output. In this case, the l/codes can be sorted by arranging the records in 3.4.2.10 numerical order.

Furthermore, descending notes can be constructed in the same way, just by reversing the logical conditions of the comparator circuit.

FIG. 6 is a block diagram of an embodiment of a sorting processor in which the sorting circuits 8 shown in FIG. 4 are connected in cascade to perform continuous parallel processing to further speed up the sorting process, thereby eliminating the need for repeated processing. be.

In the figure, 22, 23, and 24 operate on three cascaded sorting circuits.

The sorting circuit 22 includes 811 register 25, selector 2
6, S12 register 27, comparison circuit 28, selector 29
．． The sort circuit 23 consists of a selector 31, an 822 register 32, a comparison circuit 33, a selector 34, and an 823 register 35.
4 consists of selector 36,832 register 37, comparison circuit 38, selector 39,833 register 40.

Further, a counter 41 for generating a record number or key number (ID) is provided.

In the sorting circuits 23 and 24, the sorting circuit 22
The equivalent of register 25 in 811 is omitted because it is unnecessary.

Each register includes a key number (ID) part and a key part, which are transferred as a pair between the registers and input to the counter 41 at the same time.

With this configuration, the output of the sorting circuit 220 is
As in the illustrated example, the data is not stored once in the vector register, but is immediately processed continuously in the note circuit 23, and similarly, the output of the sorting circuit 23 is immediately processed by the sorting circuit 24. Therefore, in the circuit shown,
As illustrated in FIG. 7, it is possible to perform pipeline processing and complete sorting by passing four keys only once.

In order to note N keys in one process, only note circuits f and N-1 circuits need to be connected in cascade. Generally, M
When N sorting circuits are connected in series, sorting can be completed by repeating the process at least (N-1)/M times for N keys. Although the repetitive control is omitted in FIG. 6, it can be performed using the sort completion detection circuit as in FIG. 4.

In this embodiment, since the key is always processed with the key number (ID), one or both of the key and the key number can be used as appropriate as a processing result. It is possible to sort records using

〔Effect of the invention〕

As described above, according to the present invention, since note processing can be executed in a pipeline format, the program can be simplified compared to the conventional method, and the processing speed can be particularly increased when there is a large number of data to be sorted. I can do it.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of data to be sorted, Fig. 2 is a block diagram of a system according to an embodiment of the present invention, Fig. 3 is a block diagram of a sort command, and Fig. 4 is a diagram showing one implementation of a sort processor. Example circuit diagram,
Fig. 5 is an explanatory diagram of its operation, Fig. 6 is a circuit diagram of another embodiment,
FIG. 7 is an explanatory diagram of the operation. In the figure, 6 is a vector register, 7 is a sort processor, 8 is a note circuit, 9 is a sort end detection circuit, 13if: s
i register, J, 4 is a selector, 15 is an S2 register, 16 is a comparison circuit, 17 is a selector, 18 is an S3 register, 19 is an S4 register, 2o is a comparison circuit, and 21 is a flag latch. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) 5 Figure 1000 6 Figure Sfl (4) + (3) 2 (1) Yo [2] 4S12
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Claims (2)

[Claims] (1) Notes on the first, second, and third registers and the data array to be sorted into the first register! Alternatively, means for sequentially inputting data and their numbers, a comparison circuit that compares the contents of predetermined portions of the first register and the second register each time data is input to the first register, and a comparison result. is a predetermined first or second value; if it is the first value, the data in the first register is moved to the second register; Move the previous data to the third 17th register,
On the other hand, in the case of the second value, there is provided means for moving the data in the first register to the third register and retaining the previous data in the second register; a sorting circuit comprising a means for sequentially outputting data, and detecting whether or not an unsorted portion is included in the output data array obtained from the sorting circuit, and it is detected that an unnote portion is included. and means for repeatedly inputting the output data array to the sorting circuit. (2) The sorting processor according to item 1, characterized in that a plurality of sorting circuits are connected in cascade.