JPH048815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sort cell suitable for a sort processing device that applies a two-way merge sort method.

[Technical background of the invention]

One of the main processes in database processing such as a relational database is sorting processing. This sorting process involves rearranging a plurality of records in a specific file into a predetermined order according to the value of a specific field in the records. The above sorting process can also be executed by a general-purpose computer. However, since the data structure handled by a general-purpose computer and the data structure handled by database processing are essentially different, if you try to perform the above sorting process on a large amount of data that makes up a database using a general-purpose computer, the amount of data will be enormous. It takes a lot of processing time. Therefore, sorting processing apparatuses have been proposed that efficiently and exclusively perform this type of sorting processing.

One example of this type of dedicated sort processing device is Tanaka, "Trends in search/sort hardware to speed up database processing and document processing,"
"Nikkei Electronics", August 1, 1983 issue,
Merge sort type sorting processing devices such as those shown in pp. 141-178 (particularly pp. 164-165) are known. This sort processing device generally consists of a plurality of sort cells connected in cascade in multiple stages, n
The sort cell in the row is provided with a pair of buffers that store 2 ^n-1 records. For the n-th sort cell, input two sets of 2 ^n-1 records that have been sorted up to the previous sort cell, and
2 It has the function of sorting ⁿ records and outputting them to the next stage.

[Problems with background technology]

However, in the above-mentioned sorting processing device, no specific configuration for speeding up the sorting processing has been disclosed for the sorting cell, which is the main component thereof.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its object is to provide a sort cell that can perform sorting processing using a two-way merge sort method at high speed.

[Summary of the invention]

In order to achieve the above-mentioned purpose, this invention
Stores the first buffer with a capacity of 2 ^n-1 records, which stores the first sequence, and stores the second sequence.
A second buffer with a capacity for 2 ^n-1 records is provided. Addresses for the first and second buffers are specified by first and second address pointers. The contents of the first and second address pointers are saved in the first and second backup registers at the start of processing one record. Further, in the present invention, a first total record number register that holds information indicating the total number of records of the first sequence stored in the first buffer and a total number of records of the second sequence stored in the second buffer are provided. A second one that holds information indicating the number of records.
a total record number register, a first record number counter that counts the number of records output from the first buffer to the outside, a second record number counter that counts the number of records output from the second buffer to the outside; A record length register that holds information indicating the record length of a record, and a key field register that holds information that specifies a key field to be compared within the record are provided.

Data reading from the first and second buffers is performed by a reading means. The reading means reads out the first and second sequential sequences in predetermined byte units according to the first and second address pointers, and advances the first and second address pointers. Further, in the present invention, a key field detection circuit that detects whether or not read data from the first and second buffers is data in the key field indicated by the key field register, and a record end detection circuit for detecting whether the read data is the final data of a record having a record length indicated by the record length register;
A comparator for comparing data read from the buffer and selection means are provided. This selection method is
Depending on the comparison result of the comparator, the detection result of the key field detection circuit, the detection result of the record end detection circuit, and the set sorting condition, either one of the read data from the first or second buffer is selectively output. When a record end is detected by the record end detection circuit, the contents of the first or second buffer register are loaded into the first or second address pointer according to the selection result of the selection means, and output is permitted. The start address of the record that was not created is now shown.

Furthermore, in the present invention, first and second sequence output completion detection circuits are provided. The first and second sequential output completion detection circuits detect completion of output of the first and second sequential sequences according to the count results of the first and second record number counters. When the completion of output of the first or second sequence is detected by the first or second sequence output completion detection circuit, the unoutput data remaining in the second or first buffer is discharged. .

[Embodiments of the invention]

FIG. 1 shows the configuration of a sort cell 10-n (n=1, . . . m) according to an embodiment of the present invention, and FIG. The configuration of a sort processing device in which cells 10-n (n=m) are connected in cascade is shown. In the sorting cell 10-n in FIG. 1, 11U is a U (Upper) buffer register (hereinafter referred to as UB) that stores the column of records to be sorted (first sequence) input from the previous stage. ), 11L is an L (lower) buffer register (hereinafter referred to as LB) that stores a second sequence of records to be sorted (second sequence) input from the previous stage. UB11U,
11L has a capacity for 2 ^n-1 records.
12U is a U-side register counter (hereinafter referred to as ADU register) as an address pointer for UB11U, and 12L is an L-side register counter (hereinafter referred to as ADL register) as an address pointer for LB11L. 13U is
The U-side backup register (BUU register), 13L, holds the contents of ADU register 2U.
This is an L-side backup register (BUL register) that holds the contents of the ADL register 12L. 1
4 is an address signal line for UB11U and LB11L, 15 is also a data input line, and 16 is an address signal line for UB11U and LB11L.
This is a data output line from UB11U and LB11L.

17U is a U-side data register (DU register) that holds read data from UB11U, 17
L is L that holds read data from LB11L
This is the side data register (DL register). 18
are DU register 17U and DL register 17L
A comparator (CMP) that compares each content of , 19 is DU
A multiplexer (MUX) 20 that selects either the contents of the register 17U or the DL register 17L is a data output line that transmits selected output data from the MUX 19 to the next stage.

21 is the record length of the record to be sorted
RL (specifically the number of bytes that make up one record) RL
Record length register (RL register) indicating 22
is a key field length register (KL register) indicating the key field length KL (in bytes) of the key field to be compared in the sorting process. 23 is a counter (RL/KL counter) that counts the record length and key field length;
24 is a comparator (CMP) that compares the contents of the RL register 21 and the RL/KL counter 23; 25 is a comparator (CMP) that compares the contents of the RL register 21 and the RL/KL counter 23;
This is a comparator (CMP) that compares the contents of the KL register 22 and the RL/KL counter 23. 26
U is the total record number register (TRNU register) indicating the total number of records TRN of the first sort target record string stored in UB11U, and 26L is the total record number register (TRNU register).
This is a total record number register (TRNL register) that indicates the total number of records TRN of the second sort target record string stored in LB11L. 27
U is a U-side record number counter (RNU counter) that counts the number of records in the first sorting target record string, and 27L is an L-side record number counter (RNL counter) that counts the number of records in the second sorting target record string. ). 2
8U is a comparator (CMP) that compares the contents of the TRNU register 26U and the RNU counter 27U, 2
8L is a comparator (CMP) that compares the contents of the TRNL register 26L and the RNL counter 27L;
9 is a control unit that controls the entire sorting cell 10-n.

Next, the operation of the above configuration will be explained. sort·
When sorting in cell 10-n, UB11U
In the area starting from address 0, the first sort target record string from the previous stage is stored in, for example, 1 byte while maintaining its order. Also, 0 of LB11L
In the area starting from the address, the second sort target record string from the previous stage is stored in one byte unit while maintaining its order. The first sorted record column is sorted up to the previous sort cell.
2 Consists of ^n-1 records A, C, E, ...X,
The second sort target record column is
It consists of 2n ^-1 records B, D, F, ...Y sorted by cell. These records A to Y are, as shown in the format of Figure 3,
It consists of a key field, which is a comparison target part, and a non-comparison target part. In this example, it is assumed that the key field has been moved in advance so that it is positioned at the beginning of the record (see FIG. 3).
Note that the record lengths RL of records A to Y are equal.
Furthermore, the key field lengths KL of records A to Y are also equal. Here, the key field of record A is 1-byte data a, as shown in Figure 4a.
b, c, ...g, and the key field of record B is 1-byte data as shown in Figure 4b.
It is assumed that it consists of a′, b′, c′, ...g′. Also,
Assume that the non-comparison part of record A is A', and the non-comparison part of record B is B'.

Now, when starting the sorting process, ADU register 12U, ADL register 12L, RL/KL
Counter 23, RNU counter 27U, and
“0” is loaded into the RNL counter 27L. Further, the RL register 21 stores information indicating the record length RL of the record to be sorted, and the KL register 22 stores information indicating the key field length KL. Furthermore, the TRNU register 26U and TRNL register 26L have
Information indicating the total number of records TRN of the record column to be sorted is loaded.

Therefore, 1 in UB11U and LB11L
When sorting processing for records starts, at the start timing, the contents of the ADU register 12U (“0” in this example) are saved in the BUU register 13U, and the contents of the ADL register 12L (“0” in this example) are saved in the BUL register. Saved in register 13L.
In this state, first the contents of ADU register 12U are
To specify the address for UB11U,
It is controlled by the control section 29. This allows UB
Starting data a of record A (key field therein) is read from 11U. This data a is led to the DU register 17U via the data output line 16 and held in the same register 17U. At this time,
The contents of the ADU register 12U are incremented by 1, indicating the storage address of the data to be read next (b in this example). Next, the contents of ADL register 12L are LB
It is controlled by the control unit 29 to specify the address for 11L. As a result, LB11
Starting data a' of record B (the key field therein) is read from L. This data a' is led to the DL register 17L via the data output line 16,
It is held in the same register 17L. At this time,
The contents of the ADL register 12L are incremented by 1, indicating the storage address of the data to be read next (b' in this example).

DU register 17U and DL register 17L
The retained contents (a, a′ in this example) are CMP1
Guided by 8. CMP18 compares a and a'.
The comparison result of the CMP 18 is led to the control section 29.
At this time, the RL/KL counter 23 is incremented by one.
The control unit 29 includes CMPs 24, 25, 28U, 2
Comparison results for 8L are also derived.

The control unit 29 controls the DU register 17U and the DL register 1 according to preset sorting conditions and the comparison results of the CMPs 18, 24, and 25.
7L performs output control for the contents. Now, U.B.
Assuming that the read data from LB11U is U and the read data from LB11L is L, the control unit 29
If the comparison result of CMP18 is U>L or U<L, at that point the U side record (1 record in UB11U) and the L side record (1 record in LB11L)
record) and the specified key field. That is, in the case of U>L or U<L, the control unit 29 adopts the comparison result of the CMP 18 at that time as the comparison result of the designated key field. In this case, the control unit 29 controls the MUX 19 according to the above-described comparison result and sorting conditions. For example, when ascending order sorting is specified as a sorting condition, if U>L is established, the control unit 29 controls the MUX 19 so that the U side data, that is, the contents of the DL register 17L, is output up to the final data of the corresponding record. control. On the other hand, U=
In the case of L, the comparison result cannot be determined. In this case, the same result will be obtained regardless of whether the U-side data or L-side data at that time is output.
In this example, the MUX 19 is controlled so that the U-side data, ie, the contents of the DU register 17U, is selected. However, when the CMP 25 detects that the contents of the RL/KL counter 23 match the KL register 22, that is, when it is detected that the final data of the key fields are compared, the control unit 29 Confirm U=L. In this case, the control unit 2
9 controls the MUX 19 so that U-side records are selected up to the final data of the corresponding record.
Once the comparison result is determined, subsequent comparison processing is unnecessary. Therefore, it is possible to speed up the sorting process.

According to the above logic, if a=a', for example, a is selected regardless of the sorting conditions. Also, if a>a′, when sorting in ascending order,
When a' is sorted in descending order, a is selected. a
In the case of <a', the situation is the opposite of the above-mentioned case of a>a'.

When the comparison process of a and a' is completed, the next comparison process of b and b', the comparison process of c and c', etc. is performed in the same way as in the case of a and a', and the corresponding data is Selectively output. However, if a>a' or a<a', the key field comparison is determined at that point, and the subsequent output data is fixed to either the U side or the L side.

It is assumed that the above-described operation is repeated and eventually g is read from the UB 11U and g' is read from the LB 11L. g from UB11U goes to DU register 17U,
g' from LB11L is held in DL register 17L. The CMP 18 then compares g and g'. At this time, RL/KL counter 2
3 is incremented by 1, and its contents match the contents of the KL register 22. As a result, CMP25
A coincidence detection signal is outputted to the control section 29 from. When the CMP 25 detects a match, that is, when all the key fields are compared, and if all the comparison results of the CMP 18 up to that point are U=L, the control unit 29 confirms the comparison for the first time, and thereafter uses the corresponding record. U-side data is unconditionally selected up to the final data. On the other hand, if the comparison has already been confirmed, the data on the U side or the L side determined by the comparison is selected up to the final data of the corresponding record.

In this way, record A (non-comparison part A' within) or record B (non-comparison part B' within)
For example, the final data of record A is
It is assumed that the MUX 19 selectively outputs the data to the data output line 20. At this time, ADU register 12U
indicates the start address of record C, which is the next record. Further, the RL/KL counter 23 indicates the record length RL. Therefore, when outputting the final data of record A, the contents of the RL/KL counter 23 and the contents of the RL register 21 are compared.
The CMP 24 detects a match and outputs a match detection signal.

The coincidence detection signal from the CMP 24 is guided to the control section 29. Thereby, the control unit 29 determines that output of one record has ended, and performs the following processing for processing the next record. That is, the control unit 29 controls record A (i.e., U-side record), for example, as in this example.
is selected and output, the address of the current record on the L side held in the BUL register 13L (in this example, the start address of record B) is loaded into the ADL register 12L. Next, the control section 2
9 stores the contents of the ADU register 12U (in this example, the start address of record C, which is the next record on the U side) in the BUU register 13U, and the contents of the ADL register 12L in the BUL register 13L.
In addition, when the U side register is selectively output as in this example, the contents of ADL register 12L are
The process of saving in the BUL register 13L is not necessarily necessary. Further, the control unit 29 loads "0" into the RL/KL counter 23 (clears the RL/KL counter 23 to "0"), and increments the contents of the RNU counter 27U by 1. It goes without saying that when the L-side record is selected and output, the contents of the RNL counter 27L are incremented by 1. When the above operations are completed, for the next U-side and L-side records (record C and record B in this example),
The same processing as in the case of record A and record B described above is performed.

In this way, the first
It is assumed that one of the sort target record column or the second sort target record column stored in LB11L, for example, the first sort target record column, is selected and output first. At this time, the RNU counter 27U indicates the total number of records TRN. Therefore, the CMP 28U which is comparing the contents of the RNU counter 27U and the contents of the TRNU register 26U
detects a match and outputs a match detection signal when outputting the final data of the final record X of the first record string to be sorted. The coincidence detection signal from the CMP 28U is guided to the control section 29. As a result, the control unit 29 determines that the output of the first sort target record string stored in the UB 11U has ended;
Control is performed to eject unoutput data (remaining data of the second sort target record column) remaining in the LB11L. At this time, the start address of the current record held in the BUL register 13L (the L-side record that was not selected and output in the comparison process with record Then, the contents of the ADL register 12L are incremented by 1.
When the final data of record Y is output in this manner, the contents of the RNL counter 27L match the contents of the TRNL register 26L, and a coincidence detection signal is output from the CMP 28L. As a result, the control unit 29 finishes outputting the remaining data of the second sort target record string (unoutput data left in LB11L), that is, in this example, all the data for the first and second sort target record strings are output. Determine the end of the sorting process and stop the sorting operation.

In the above embodiment, the specified key field, which is the comparison target section, is moved to the beginning of the record, but the present invention is not limited to this. However, if the specified key field is not located at the beginning of the record, information specifying the start and end positions of the key field within the record is required. In addition, in this case, it is impossible to determine whether to selectively output U-side or L-side data, at least from the first data of the record to the data immediately before the key field, so these U-side and L-side data are temporarily stored. A buffer is required. The above embodiment can be said to be a case where the start position of the key field matches the start position of the record.

〔Effect of the invention〕

As described in detail above, according to the present invention, comparison between specified key fields can be performed efficiently, and the comparison result can be determined at least by the final data of the specified key field, so that subsequent comparison processing is not necessary. Therefore, sort processing using the two-way merge sort method can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a sort cell according to an embodiment of the present invention, and FIG. 2 is a block diagram of a sort cell according to an embodiment of the present invention.
An overall configuration diagram of a sort processing device using cells; FIG. 3 is a diagram showing the record format;
FIG. 4 is a diagram showing an example of record contents. 11U...UB (U Batsuhua), 11L...LB
(L buffer), 12U...ADU register, 12
L...ADL register, 13U...BUU register, 13L...BUL register, 18, 24, 2
5, 28U, 28L...CMP (comparator), 19...
...MUX (multiplexer), 21...RL register, 22...KL register, 23...RL/KL counter, 26U...TRNU register, 26L...
...TRNL register, 27U...RNU counter,
27L...RNL counter.

Claims (1)

[Claims] 1 Input two sets of 2n ^-1 records that form a sequence from the previous stage, and set a sort cell n (n=1,...m) to sort the ²ⁿ records and output them to the next stage.
(m is an integer greater than or equal to 1) In a two-way merge sort type sort processing device formed by cascading stages, a first buffer having a capacity of 2 ^n-1 records for storing a first sequence; a second buffer having a capacity of 2 ^n-1 records for storing a second sequence;
a first address pointer that specifies an address for the first buffer; a second address pointer that specifies an address for the second buffer;
a first backup register for storing the contents of the first address pointer at the start of processing of one record; a second backup register for storing the contents of the second address pointer at the start of processing for one record; The above first data stored in one buffer
a first total record number register that holds information indicating the total number of records of the ordered sequence; and a second total record number register that holds information indicating the total number of records of the second sequence stored in the second buffer. register and
A first record number counter that counts the number of records output from the first buffer to the outside, a second record number counter that counts the number of records output from the second buffer, and a record length of the record. a record length register that holds information that specifies a key field to be compared in the record, a key field register that holds information that specifies a key field to be compared in the record, and a record length register that holds information that specifies a key field to be compared in the record, and a read means for reading out the first and second sequences in predetermined byte units and advancing the first and second address pointers, and the read data from the first and second buffers being indicated by the key field register. a key field detection circuit that detects whether or not the data is in the key field;
a record end detection circuit that detects whether the data read from the buffer is the final data of a record with the record length indicated by the record length register; and a comparator that compares the data read from the first and second buffers. and the first or second one according to the comparison result of this comparator, the detection result of the key field detection circuit, the detection result of the record end detection circuit, and the set sorting condition.
a selection means for selectively outputting either one of the read data from the buffer; and when the record end detection circuit detects the end of the record, according to the selection of the selection means, one of the first or second address pointer; means for loading the contents of the first or second backup register;
means for updating either the first record number counter or the second record number counter according to the selection of the selection means when the record end detection circuit detects a record end; and a count of the first record number counter. Depending on the results,
A first device that detects the completion of external output of the first ordered sequence.
a sequence output completion detection circuit; a second sequence output completion detection circuit for detecting completion of external output of the second sequence according to the count result of the second record counter; A sort cell characterized by comprising means for discharging unoutput data remaining in the second or first buffer according to the output completion detection result by the column output completion detection circuit.