JPS6162134A - Sort preprocessor - Google Patents

Abstract

PURPOSE:To speed up the sort processing and to make a buffer memory unnecessary by applying the processing to a sort object record and transferring the specified key field to the forefront of the record. CONSTITUTION:First, the initializing processing is carried out, and a sort object record is led to a memory 11. Under the control of a control circuit 24, the writing in the memory 11 in accordance with a write address WA from an address register 14 is carried oyut. Then the circuit 24 controls a multiplexer 18, and makes it select a read commencement address IAP from an IPA register 16, thereby setting this to an address register 15. The circuit 24 controls a multiplexer 19, and switches the address WA with respect to the memory 11 into an read address RA, thereby controlling the reading with respect to the memory 11. The register 15 is added by one at each byte reading. Thus, the record written in the memory 11 is read out on a data line 13 by the unit of one byte sequentially from the forefront byte of the key field, and then led to a sort processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a saw 1 to a preprocessing device that performs preprocessing on records to be sorted, particularly in order to improve the efficiency of sorting.

[Technical Background of the Invention] One of the main processes in database processing such as a relational database is sorting processing. This sorting process is
It is to arrange a plurality of records in a specific file in a predetermined order according to the values of specified key fields in the records. The sorting process described above can also be executed on a general-purpose computer (511). , August 1, 1983 issue,
pp.

141-178 (particularly pp, 164-
Merge sort type sorting processing devices such as No. 165, ) are known. This sort processing device generally consists of a plurality of sort cells connected in cascade in multiple stages. The n-th sorting cell has the function of inputting two sets of 2n -1 records that have been sorted up to the previous sorting cell, sorting the 2n records, and outputting them to the next stage. There is. In this sort cell sorting process, one record is selected from each set in the order of input, and two
The key fields are compared between the records, and the record to be output is determined according to the comparison result.

For this reason, the above-mentioned sorting processing apparatus has a major drawback. Another disadvantage is that it takes a long time to complete the comparison of key fields after the specified key field is entered, reducing the sorting processing speed.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to perform preprocessing on records to be sorted and move a designated key field to the beginning of the record.
To provide a sort preprocessing device that can perform comparison processing at the head of a record in sorting processing, speed up the sorting processing in the sorting processing device, and eliminate the need for memory for buffering data preceding a key field. There is a particular thing.

The data that has been compared and contrasted in the sorting process (that is, the record in which the specified key field has been moved to the beginning) is supplied to the sorting processing device as data (record) to be sorted.

[Embodiment of the Invention] FIG. 1 shows the configuration of a sorting preprocessing device according to an embodiment of the invention. This pre-sorting device is placed on the input side of the sorting device. In FIG. 1, 11 is a memory for temporarily storing data for the code to be sorted; 12 is a data input line connected to the memory 11;
13 is a data output line connected to the memory 11. 14 is an address register that holds a write address WA for the memory 11, and 15 is an address register that holds a read address RA for the memory 11. Address register 14. Is has a counter function.

16 is the read start address IAP for the memory 11)
This is an adder that performs addition of and -1. 18 is Fusa, 1
9 is the contents of address registers 14 and 15 (WA, RA
) as the address for the memory 11.

20 is the record length R of the record to be sorted
8Z (actually R3Z-1, unit is byte); 21 is a comparator that compares the contents (WA, R8Z) of the address register 14 and size register 20 to detect a match.

22 is an address register 15 and a size register 20
23 is an address register 15 and a -1 circuit 17.
A comparator 24 is a control circuit that compares each content (RA, IAP-1) of the data and detects a match. The control circuit 24 controls the switching of the multiplexers 18 and 19 in response to the coincidence detection signals from the comparators 21 to 23, and further performs a termination interrupt to a host device (not shown).

, the address register 14 is cleared by
1;-1 The read start address rAP is set in the A'P register 16. This read start address IAP uses information indicating the data to be compared in each record to be sorted, that is, the position of the key field (byte position from the beginning of the record).

Furthermore, the record length R8Z of the record to be sorted is set in the size register 20. When the above initialization processing is performed, records to be sorted are led to the memory 1 via the data input line 12 h1.

Therefore, under the control of the control circuit 24, the multiplexer 19 selects address register 4 of the address registers 4.15, and based on the write address WA from the address register 14, a write operation to the memo 1 to 11 is performed. will be carried out. The address register 14 is incremented by 1 every time one byte is written, and when the record on the data input line 12 is placed one byte 1-11 in the continuous area starting from address "0" in memory 1, this fact is sent to the control circuit 24. Notice. Control port! 1; When a match is notified from the comparator 21 in the record write mode to the memory, the path 24 determines that the last byte of the -rou code is to be written;
Write mode force at the end of that cycle
Change to l+ read mode. At this time, memo 1 no. 11
The area from address rOJ to address rR8Z-IJ (O police,
As shown in FIG. 2(a), the data for the code is written. Furthermore, the first byte of the (specified) key field in the record is written to address rIAPJ.

In the read mode, the control circuit 24 first controls the multiplexer 18 to select the read start address IAP from the read start address IAP from the IAP register 16 or the fixed value "0" (address indicating address 0), The same IAP is set in the address register 15. Note that this operation can also be performed at the time of the above-mentioned initialization.Then, the control circuit 24 controls the multiplexer 19 to set the address for the memory 11 in the address register 15. It is guided by a three-dimensional system (not shown).

Knee "11. Comparator 22. At' L/2 L/,
:), 915 Ka, et al., 7) Read.

Records from address RA and size register 20.

The length R8Z is compared, and when RA matches R8Z, the control circuit 24 is notified of this fact. The control circuit 24 is
When a match is notified from the comparator 22 in the record read mode from the memory 11, it is determined that the last byte of the Lou code is to be read, and the multiplexer 18 is switched and controlled. Then, the control circuit 24 causes the address register 15 to be set to the newly selected fixed value "0" from the multiplexer 18 at the end of that cycle. As a result, the read address RA for the memory 11 returns to address rOJ, and data is read out in 1-byte units starting from address "0" in the memory 11. That is, when it is detected that the last byte of the record (from the first byte of the key field) is read, the next read is performed. The output value from the -1 circuit 17 is +! -'p:
The read start address 11, which is the content held in the star 16: 'IAP-1, which is obtained by subtracting 1 from AP. Comparator 23
1. :.

1.'1, upon detecting that RA matches IAP-1, notifies the control circuit 24 of this fact. Control circuit 24
When a match is notified from the comparator 23 in the mode of reading records from memory 1, it determines that the byte immediately before the key field is to be read, and in the next cycle it indicates to the host device that processing of the roux code has ended. Issues an interrupt and stops reading from memory 1. Then, in the sort preprocessing device shown in FIG. 1, according to instructions from the higher-level device,
The preprocessing for the next roux code is performed again.

As described above, in the sort preprocessing device shown in FIG.
The data from the byte position indicated by AP to the end of the record, that is, from the first byte of the specified key field in the record to be sorted to the last byte of the record, is read and output in units of 1 byte, and then the remaining data is read out. data, that is, the moved records to be sorted are supplied.

Note that in the above example, the key field first is ←
Read from the byte to the last byte of the record! Next, the case of reading from the first byte of the record to the byte immediately before the key field has been described, but the present invention is not limited to this. For example, you may first read the key field, then read from the first byte of the record to the byte immediately before the key field, and finally read from the next byte of the key field to the last byte of the record. Processing may be performed so that the field is moved to the beginning of the record. However, in this case, a register that holds the field length VDL of the specified key field, a means for detecting that the last byte of the key field is read based on the contents of this register and the read address RA, and furthermore, When reading from the byte, a means for setting IAP+VDL as the read address RA is required.

[Effects of the Invention] As described in detail above, according to the present invention, by supplying the information to the sorting processing device, the sorting processing device can quickly determine the comparison results of the key fields, thereby improving the sorting processing speed. Furthermore, since the key field is located at the beginning of the record, there is no need to hold data (not to be compared) until the key field arrives, as in the past, and therefore no buffer memory or the like is required. Note that the comparison of key fields between 2111 records is performed in predetermined byte units from the beginning until the comparison result is finalized, but when the values are equal, 2
Since comparison data from any of the records may be output, there is no need to hold the compared data for which a match has been determined until the comparison result is finalized. Therefore, there is no problem when the sort processing device does not have the buffer 7 memory described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pre-sorting device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating the operation of the device shown in FIG. 11...Memory, 14.15...Address register, 16...IAP register, 20...Size register, 18.19...Multiplexer, 21-23...
- Comparator, 24... control circuit.

Claims (1)

[Claims] A memory that stores one record's worth of data to be sorted in a continuous area starting from a predetermined address, and a read access to this memory in order from the address corresponding to the start position of the specified key field to be compared in sorting. and a second reading means for reading the remaining data in the memory, and supplies the data read from the memory to a sorting processing device as data to be sorted. A sorting preprocessing device characterized by: