JPH0772879B2 - Cache memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct map type or set associative type cache memory device used as a high speed local memory of an electronic computer.

2. Description of the Related Art FIG. 3 shows an example of a schematic configuration of a conventional cache memory device. An address is newly input to the cache address register 4, and the output of this address lower part 10 is the tag part 1
Is input to the address decoder 3 provided in common to the data section 2. The decoded data of the tag unit 1 is input to the comparator 6, and the upper address of the cache register 4 is stored.
Compared with 11. The data output 14 decoded and output from the data section 2 is controlled by the gate 7 according to the comparison result.
Is output as valid data to the arithmetic unit.

In the tag section 1, the tag field section of the used address is cached in the tag section 1 and the corresponding data is cached in the data section 2 in advance. Therefore, once used data is cached, there is no need to access an external main storage device, which is slower than the internal memory. Moreover, this eliminates the need to frequently use the data bus connecting the external main memory device and the arithmetic unit.
Therefore, in general, improvement in calculation efficiency can be expected.

However, a data miss hit (when there is no newly addressed used data in the cache memory device) results in an update of the cache data.

This process will be described below with reference to the timing chart of FIG. Now the driving clock is 100nse per machine cycle
It is a 4-phase clock of c.

The cache address register 4 changes at the second clock. Therefore, the tag unit 1 and the data unit 2 are precharged (initialized) during the second clock period.

Next, at the third clock, the lower address part 10 is input to the address decoder 3, and the outputs of the tag part 1 and the data part 2 are read at the 0th clock.

The comparator 6 compares the output from the tag unit 1 with the upper address part 11 of the address. If the results match, the data output 14 is output to the arithmetic unit via the gate 7 as valid data.

On the other hand, if they do not match, the mishit signal is output slightly behind the 0th clock. In response to this, the valid data (n + 1) of the external main memory is input to the arithmetic unit and the cache memory unit.

Here, if a high-speed main memory device having an access time of 40 to 50 nsec is used, the valid data (n + 1) can be fetched in the latter half of the third clock and the data can be written in the data section 2 at the 0th clock.

However, the access to the address (n + 2) by the cache memory device after this mishit is performed after writing valid data (n + 1) in advance. Therefore, a time lag occurs between the precharge period and the write period of the first clock due to the 0th clock dakuwrite enable signal and the data write enable signal.

That is, if a mishit occurs, it takes one machine cycle, that is, an extra calculation time of 100 nsec, for updating the cache memory device. In particular, when this mis-hit occurs frequently, it causes a large loss of calculation time.

Problems to be Solved by the Invention As described above, in the conventional cache memory device, there is a problem that a time lag occurs due to update of cache data when a mishit occurs. This is because if you do not consider the data bus occupation problem associated with data transfer, using a high-speed main memory device instead of configuring a cache memory will not cause a time lag due to writing to the cache memory device. Can even be sent to a computing device. Therefore, eliminating this time lag is an extremely important issue for improving the performance of the cache memory device.

The present invention has been made in view of the above problems, and an object thereof is to newly propose a high-performance cache memory device with no time lag.

The present invention provides a cache address register that temporarily stores address data, a latch circuit that receives a first portion of the output of the cache address register as an input, and an output of the latch circuit as an input. A first address decoder, a data section memory decoded by the first address decoder, a gate circuit for controlling the output of the data section memory to the arithmetic unit, and a control signal for the gate circuit. The comparison circuit, a tag section memory for outputting comparison data to one input of the comparison circuit, and a second address decoder for decoding the tag section memory are provided, and the second part of the output of the cache address register is The first portion of the output of the cache address register is coupled to the other input of the comparison circuit and The cache memory device is characterized by being inputted to the second address decoder.

The working address data is temporarily stored in the cache address register. The first portion of the output of the cache address register is input to the second address decoder and decodes the data in the tag memory. This data is compared with the second part of the cache address register by the comparator and outputs a match / mismatch signal.

On the other hand, the first part of the output of the cache address register is delayed by a desired time by a latch circuit. Therefore, the output of the data section memory decoded by the first address decoder connected to this latch circuit is delayed. Therefore, the output of the data memory is delayed as compared with the coincidence / non-coincidence signal from the comparator.

Therefore, the delay time secures the time for replacing the output of the data unit memory with the data from the main storage device when the non-match signal is issued and for writing the data in the data unit memory. That is, it is possible to eliminate the time lag due to reading and writing from the main storage device.

Embodiment FIG. 1 shows a schematic configuration of a cash memory device in an embodiment of the present invention. A new address is newly input to the cache address register 4, and the output of the lower address section 10 is input to the first address decoder 3a and the second address decoder 3b provided in the tag section 1 and the data section 2, respectively. . Here, the difference from the prior art is that the decoding of the data section 2 is performed via the latch circuit 5. The decoded tag output 12 of the tag unit 1 is input to the comparator 6,
It is compared with the upper address part 11 of the cash register 4. Based on the comparison result, the gate 7 is controlled to determine whether to output the data output 14 decoded and output from the data section 2 to the arithmetic unit as valid data. At the same time, the hit / miss hit signal 16 is also output. At the time of a mishit, the address upper part 11 is directly written in the tag part 1, and further the data input 15 is written in the data part 2 from the main memory 8 through the data bus 9.

The process of hit / miss hit will be described below with reference to the timing chart of FIG. The driving clock is a 4-phase clock with 100 nsec per cycle.

The cache address register 4 changes at the second clock. Here, the tag unit 1 is precharged (initialized) during the period of the second clock. Next, at the third clock, the lower address part 10 is input to the second address decoder 3b, and the tag output 12 is read at the zeroth clock. On the other hand, with respect to the data section 2, since the latch circuit 5 is turned on at the first clock, precharging is performed at this timing, the data is input to the address decoder 3a at the second clock, and the data output 14 is read at the third clock. That is, the data output 14 is output with a delay of three layers (75 nsec) from the tag output 12.

The comparator 6 compares the output from the tag unit 1 with the upper address part 11 of the address. If the results match, the data output 14 is output to the arithmetic unit via the gate 7 as valid data. That is, the tag unit 1 and the data unit 2 can be read in 100 nsec, that is, in one cycle.

On the other hand, for example, when a mismatch occurs at the address (n + 1),
The mishit signal is output slightly after the 0th clock. In response to this, the valid data (n + 1) in the main memory 8 is input to the cache memory device and the arithmetic device in the middle of the third clock.

Further, at the 0th clock, valid data (n + 1) is written in the data section 2 by the data write enable signal.
Further, regarding the data update of the tag part, the tag write enable signal becomes low at the first clock after the above-mentioned mishit signal is generated, and the data of the address upper part 11 is written.

Then, the data at the address (n + 2) is input to the cache address register 4. At this time, with respect to the tag unit 1, the data is already rewritten at the first clock, precharged at the second clock, decoded at the third clock, and output at the 0th clock. Similarly, with respect to the data section 2, rewriting of data due to a mishit has already finished at the 0th clock. Therefore, it is precharged at the next first clock, decoded at the second clock, and output at the third clock. Therefore, (n + 1)
There is no time lag in accessing the data at the next (n + 2) address due to the data hit at the address.

Therefore, it is possible to apparently eliminate the time lag due to the data replacement in the cache memory device. Therefore, when the mishit occurs N times, the execution time is conventionally delayed by N × 100 nsec, but this can be eliminated.

Advantageous Effects of the Invention By configuring the address decoder independently for each of the tag portion and the data portion that configure the cache memory device and providing the latch circuit, the data portion read can be delayed from the tag portion read. Therefore, the tag part operation and the data part operation can be pipelined, and the update time of the data part can be apparently eliminated. Even after a miss hit, you can operate continuously without overhead.

Therefore, the cache memory device of the present invention is extremely useful for speeding up calculations.

[Brief description of drawings]

1 is a schematic configuration diagram of a cache memory device according to an embodiment of the present invention, FIG. 2 is an operation timing chart diagram of the same device, FIG. 3 is a schematic configuration diagram of a conventional cache memory device, and FIG. It is an operation timing chart of the device. 1 ... Tag part, 2 ... Data part, 3a ... First address decoder, 3b ... Second address decoder, 4 ... Cache address register, 5 ... Latch circuit, 6 ... Comparator, 7 ...... Gate, 10 ...... Lower address part, 11 ...... Higher address part.

Claims (1)

[Claims] 1. A cache address register for temporarily storing address data, a latch circuit for receiving a first portion of an output of the cache address register as an input, and a first address decoder for receiving an output of the latch circuit as an input. A data section memory decoded by the first address decoder, a gate circuit for controlling the output of the data section memory to the arithmetic unit, a comparison circuit for outputting a control signal to the gate circuit, and the comparison circuit. A tag section memory for outputting comparison data to one input of the cache address register; and a second address decoder for decoding the tag section memory. And the first portion of the output of the cache address register is coupled to the second address decoder. Cache memory device according to claim entered to become.