JPS63206843A - Cache memory device - Google Patents

Abstract

PURPOSE:To eliminate the update time of a data part in appearance, by constituting address decoder parts on a tag part and the data part which constitutes a cache memory independently, and delaying the readout of the tag part later than the data part by providing a latch circuit. CONSTITUTION:An address data is stored in a cache register 4 transiently, and an address high-order part 11 is inputted to second decoder, and the data of the memory of the tag part 1 is decoded. The data is compared with an address low-order part 10 by a comparator 6, and a coincidence and a discrepancy signals are issued. Meanwhile, since the address low-order part 10 is delayed for a desired time by the latch circuit 5, the output of the memory of the data part decoded at first decoder 3a is delayed later than the output of the comparator 6. Therefore, the output of the memory of the data part is replaced by the data from a main memory device 8 by the discrepancy signal, and furthermore, a time to write the data on the memory of the data part 2 is secured by the above stated delay time, and the operations of the tag part and the data part are made into a pipeline, and the update time of the data part can be eliminated is appearance, and a continuous operation can be performed even after mis-hit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a direct map type or set associative type cache memory device used as a high-speed local memory of an electronic computer.

2. Description of the Related Art A schematic example of a conventional cache memory device is shown in FIG. A new address is input to the cache address register 4, and the output of this address lower part 10 is sent to the address decoder 3 provided in common to the tag part 1 and data part 2.
is input. The decoded data of the tag section 1 is input to the comparator 6 and compared with the upper address section 11 of the cash register 4. Based on the comparison result, the gate 7 is controlled to determine whether or not the data output 14 decoded and outputted from the data section 2 is outputted to the arithmetic unit as valid data.

In this tag section 1, the tag field section of the used address is cached in advance in the tag section 1, and the data corresponding thereto is cached in the data section 2.

Therefore, once used data is cached, there is no need to access the external main storage device, which is slower than the internal memory. Furthermore, this eliminates the need to frequently use the data bus that connects the external main storage device and the arithmetic unit.

Therefore, improvement in calculation efficiency can generally be expected.

However, a data miss (when the newly addressed used data does not exist in the cache memory device) causes an update of the cache data.

This process will be explained below based on the timing chart of FIG. Currently, the driving clock is 100 machine cycles.
A 4-phase clock of nsec is used.

Cache address register 4 changes on the second clock. Therefore, tag section 1 and data section 2 are precharged (initialized) during this second clock period.

Then, at the third clock, this address lower part 1O is input to the address decoder 3, and the tag part 1 and the data part 2 are inputted to the address decoder 3.
The output of is read out at the 0th clock.

The output from the tag unit 1 and the address upper part 11 of the address are compared by a comparator 6.

If the results match, the data output 14 is output as valid data to the arithmetic unit via the gate 7.

On the other hand, in the case of mismatch, a mishit signal is output with a slight delay after the 0th clock. In response to this, valid data (n+1) in the external main storage device is input to the arithmetic unit and cache memory device.

Here, if a high-speed main memory device with an access time of 40 to 50 nsec is used, the valid data (n+1) can be fetched in the latter half of the third clock, and this data can be written to the data section 2 at the 0th clock. I can do it.

However, after this miss, the cache memory device accesses the address (n+2) after writing valid data (n+1) in advance. Therefore, a time lag occurs between the precharge period due to the tag write enable signal and data write enable signal of the 0th clock and the write period of the 1st clock.

In other words, when a miss occurs, it takes one machine cycle, or 100ns, to update the cache memory device.
This will require additional calculation time for c. In particular, if this mishit occurs frequently, it will cause a large loss of calculation time.

Problems to be Solved by the Invention As described above, in the conventional cache memory device, there is a problem in that when a miss occurs, a time lag occurs due to updating of cache data. This means that if you do not take into account the problem of data bus occupancy associated with data transfer, it is better to use a high-speed main storage device instead of configuring a cache memory to quickly transfer the necessary data without the time lag caused by writing to the cache memory device. It is even conceivable that the data could be sent to a computing device. Therefore, this time lag (
This is an extremely important issue for improving the performance of cache memory devices.

The present invention was made in view of such problems, and an object of the present invention is to newly propose a high-performance cache memory device without time lag.

Means for Solving the Problems The present invention provides a cache address register that temporarily stores address data, a latch circuit that receives the first part of the output of this cache address register, and a latch circuit that receives the output of this latch circuit as input. a first address decoder, a data section memory decoded by the first address decoder, a gate circuit that controls output of the data section memory to the arithmetic unit, and a control signal output to the gate circuit. A comparison circuit, a tag part memory that outputs comparison data to one input of this comparison circuit, and a second address decoder that decodes this tag part memory,
A second portion of the output of the cache address register is coupled to the other input of the comparison circuit, and the first portion of the output of the cache address register is input to the second address decoder. It is a cache memory device that

Working address data is temporarily stored in a cache address register. A first portion of the cache address register output is input to a second address decoder to decode the data in the tag memory. This data is compared with the second portion of the cache address register by a comparator and outputs a match or mismatch signal.

On the other hand, the first portion of the output of the cache address register is delayed by a desired amount of time by a latch circuit. Therefore, the output of the data portion memory decoded by the first address decoder connected to this latch circuit is delayed. Therefore, the output of this data portion memory is delayed compared to the match/mismatch signal from the comparator.

Therefore, the delay time ensures the time required for a mismatch signal to be generated, the output of the data section memory to be replaced with data from the main memory, and further written to the data section memory. In other words, it is possible to seemingly eliminate the time lag caused by reading and writing from the main memory.

Embodiment FIG. 1 shows a schematic configuration of a cache memory device according to an embodiment of the present invention. A new address is input to the cache address register 4, and the output of this address lower part 10 is sent to the first address decoder 3a and second address decoder 3 provided in the tag part 1 and data part 2, respectively.
b. Here, the difference from the conventional method is that the data section 2
is decoded via the latch circuit 5.

The decoded tag output 12 of the tag unit 1 is input to the comparator 6 and compared with the upper address part 11 of the cash register 4. Based on this comparison result, gate 7 is controlled,
It is determined whether the data output 14 decoded and outputted from the data section 2 is outputted to the arithmetic unit as valid data. At the same time, a hit/miss signal 16 is also output. In the event of a mishit, the upper part 11 of the address is written directly into the tag part 1, and furthermore, the data input 15 is written into the data part 2 from the main memory 8 through the data bus 9.

This hit/miss process will be explained below based on the timing chart of FIG. The driving clock is a four-phase clock with one cycle of 100 nsec.

Cache address register 4 changes on the second clock. Here, the tag section 1 is precharged (initialized) during this second clock period. Next, this address lower part 10 is input to the second address decoder 3b at the third clock, and the tag output 12 is read out at the O-th clock. On the other hand, regarding the data section 2, since the latch circuit 5 is rendered conductive at the first clock, it is precharged at this timing and is input to the address decoder 3a at the second clock, and the data output 14 is read out at the third clock. In other words, this data output 14 is more 3-phase than the tag output 12 (
output with a delay of 75 nsec).

The output from the tag unit 1 and the address upper part 11 of the address are compared by a comparator 6.

If the results match, the data output 14 is output as valid data to the arithmetic unit via the gate 7. That is, both the tag section 1 and the data section 2 can be read out in 100 nsec, that is, in one cycle.

On the other hand, if a mismatch occurs at address (n+1), for example,
The mishit signal is output with a slight delay after the 0th clock. In response to this, the valid data (n+ 1) in the main memory 8
is input to the cache memory device and the arithmetic unit in the middle of the third clock.

Further, at the Oth clock, valid data (n+1) is written into the data section 2 by the data write enable signal.

Regarding updating of data in the tag section, the tag write enable signal becomes low at the first clock after the above-mentioned miss signal is generated, and data in the upper address section 11 is written.

Next, the data at address (n+2) is input to the cache address register 4. At this time, data has already been rewritten in the tag section 1 at the first clock, precharged at the second clock, decoded at the third clock, and output at the Oth clock. Also, data section 2
Similarly, data rewriting due to a miss has already been completed at the Oth clock. For this reason, the first
It is precharged by the clock, decoded by the second clock, and outputted by the third clock. Therefore, a mishit in the data at address (n+1) will not cause a time lag in accessing the data at the next address (n+2).

Therefore, it is possible to eliminate the apparent time lag due to data replacement in the cache memory device.For this reason, when a miss occurs N times, there was a delay in execution time of NX100nsec, but this can be eliminated. I can do it.

Effects of the Invention By configuring address decoders independently in the tag section and the data section constituting the cache memory device and providing a latch circuit, it is possible to delay reading the data section from reading the tag section. Therefore, the tag section operation and the data section operation can be pipelined, and the update time of the data section can be seemingly eliminated. Even immediately after a mishit, operations can be performed continuously without overhead.

Therefore, the cache memory device of the present invention is extremely useful for speeding up calculations.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the configuration of a cache memory device according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the same device, FIG. 3 is a schematic diagram of the configuration of a conventional cache memory device, and FIG. 4 is the same diagram. FIG. 3 is an operation timing chart of the device. DESCRIPTION OF SYMBOLS 1... Tag part, 2... Data part, 3a... First address decoder, 3b... Second address decoder, 4... Cache address register, 5... Latch circuit, 6 ...Comparator, 7...Gate, 1o...
Address lower part, 11...address upper part. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 3

Claims (1)

[Claims] a cache address register that temporarily stores address data; a latch circuit that receives a first portion of the output of the cache address register; a first address decoder that receives the output of the latch circuit;
a data section memory decoded by the address decoder, a gate circuit that controls the output of this data section memory to the arithmetic unit, a comparator circuit that outputs a control signal to this gate circuit, and one input of this comparator circuit. a tag section memory for outputting comparison data; and a second address decoder for decoding the tag section memory; a second portion of the output of the cache address register is coupled to the other input of the comparison circuit; A cache memory device, wherein the first portion of the output of the cache address register is input to the second address decoder.