JP3052952B2 - Data retrieval device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data retrieval apparatus for retrieving data at high speed in an electronic computer.

[0002]

2. Description of the Related Art As shown in FIG.
It comprises a central control circuit 2 and a central control storage circuit 6. Here, when performing a data search, data is read one by one from the central control storage circuit 6 and compared with the search data to search for sequentially matching data.

Therefore, when collating all data with search data, it takes a lot of time to read all data. For example, if 1 megabyte of data is processed at a calculation speed of 1 mips, (1) read address calculation , (2) reading, (3) comparison with search data, and (4) conditional branching, the search was repeated, and as a result, a search time of about 4 seconds was required.

[0004]

As described above, there is a drawback that the processing speed is slow when a calculation is repeated using a conventional electronic computer to repeat the association such as application to artificial intelligence.

[0005] An object of the present invention is to provide a data retrieval apparatus with a high processing speed, excluding such a conventional disadvantage.

[0006]

The data retrieval apparatus of the present invention comprises a central control circuit connected to an address bus and a data bus and having a control signal terminal for outputting a data control signal; and an address terminal connected to the data bus. A first storage circuit having a data terminal connected to the data bus via a first buffer register circuit, an address terminal connected to the address bus, and a data terminal connected to the data bus via a second buffer register circuit; And a first buffer circuit in which a data terminal of the second storage circuit and the data terminal of the first storage circuit are connected to an input and an output is connected to a data terminal of the second storage circuit. A dedicated circuit having a second buffer circuit whose input is connected to the output and whose input is connected to the address bus, wherein each of the first and second buffers is provided. Connected control store write control signal to the terminals of § circuit, the first, storage read control signal to the control terminal of the second respective buffer register circuit are connected,
A value of an address bus via the second buffer circuit is stored at an address specified by the data bus in the first storage circuit, and the first storage circuit reads data at an address specified by the data bus. The read data is stored in the second storage circuit at an address designated by the address bus.
And the value of the address bus before the value of the data bus has the same value is stored in the second storage circuit.

[0007]

FIG. 1 is a block diagram showing an embodiment of a portion including a dedicated circuit 1 of a data search apparatus according to the present invention. The dedicated circuit 1 of the present embodiment includes first and second storage circuits 24 and 25 and first and second buffer register circuits 29,
33. The dedicated circuit 1 connects the data bus 4
It is connected to the address terminal bundle 24-1 of the first storage circuit 24, and the address bus 3 is connected via the second buffer circuit 26.
It is connected to the data terminal bundle 24-2 of the first storage circuit 24. The control terminal of the second buffer circuit 26 is connected to the storage write control signal 28. Connect the address bus 3 to the address terminal bundle 25-1 in the second memory circuit 25, a data terminal bundle 24-2 of the first storage circuit 24 through the first buffer circuit 27 the second memory circuit 25 Data terminal bundle 25-
Connect to 2. The control terminal of the first buffer circuit 27 is connected to the storage write control terminal. First storage circuit 24
Are connected to the data bus 4 via the first buffer register circuit 29.

[0008] The read control terminal of the first buffer register circuits 29 connected to the output terminal of the address decode circuit 35, connects the memory read control signal 32 to the writing control terminal. Also, the data terminal bundle 25-2 of the second storage circuit 25
Are connected to the data bus 4 via the second buffer register circuit 33. The read control terminal of the second buffer register circuit 33 is connected to the output terminal of the address decode circuit 36, and the write control terminal is connected to the storage / read control signal 32.

[Write Operation] (Procedure 1) The central control circuit 2 outputs a write data value DT to the data bus 4 and outputs a data address value ADR to the address bus 3. Writing from the first storage circuit 24
Storage address DT of storage circuit 24 specified by data value DT
Is read out from the first buffer circuit 2
7, and is stored in the storage address ADR of the second storage circuit 25. The value ADR2 read from the first storage circuit 24 is the data of the past write data having the same value DT as the data value DT.
Data address value. In this manner, the address value ADR2 of the past data having the same value as the write data value DT is stored in the storage address ADR of the second storage circuit 25.

(Procedure 2) The write data value DT is output to the data bus 4 and the data address value ADR is output to the address bus 3.
Is output. The storage circuit 24 stores the value ADR of the address bus 3 at the storage address DT via the buffer circuit 26.
Thus, the data address value ADR is stored in the storage address DT of the storage circuit 24.

[Read Operation] (Procedure 1) The central control circuit 2 outputs the search data value DT to the data bus 4 and reads the address value ADR of the search data DT from the storage address DT of the storage circuit 24 to the buffer register circuit 29. Remember.

(Procedure 2) The central control circuit 2 outputs the specified address of the buffer register circuit 29 to the address bus 3 so that the address value ADR is read from the buffer register circuit 29 to the data bus 4. Thereby, the search data DT
Is obtained.

(Procedure 3) The central control circuit 2 uses the storage circuit 25
Is read out and stored in the buffer register circuit 33. This data value ADR2 is another address value of the search data DT.

(Procedure 4) The address value ADR2 is read from the buffer register circuit 33 to the data bus 4 by outputting the designated address of the buffer register circuit 33 to the address bus 3. Thus, the past address value ADR2 of the search data DT is obtained.

(Procedure 5) Further, with respect to the address value ADR2, steps 3 to 4 are repeated similarly to the address value AR, and the past address values of the search data DT are read out one after another.

The present embodiment has an advantage that the dedicated circuit 1 can be easily constituted by a combination of an existing storage circuit and a buffer circuit. In addition, when searching for an address of data to be searched, storage is performed several times in a short time. There is an advantage that reading can be performed and high-speed operation is possible. Also, for example, in this embodiment,
Using a memory circuit (24) with a calculation speed of 1 mips,
Data retrieval can be performed several microseconds and several million times faster than before.

[0017]

As described above, according to the present invention, since the address of the storage circuit corresponding to the search data can be directly read, there is an effect that high-speed data search can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional data search device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dedicated circuit 2 Central control circuit 3 Address bus 4 Data bus 5 Control signal 6 Central control storage circuit 24, 25 Storage circuit 24-1, 25-1 Address terminal bundle 24-2, 25-2 Data terminal bundle 26, 27 Buffer circuit 28 Storage write control signal 29,33 Buffer register circuit 32 Storage read control signal 35,36 Address decode circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/30 G11C 15/04

Claims (1)

(57) [Claims] A central control circuit connected to an address bus and a data bus and having a control signal terminal for outputting a data control signal; and an address terminal connected to the data bus and connecting the data terminal via a first buffer register circuit. A first storage circuit connected to the data bus, a second storage circuit having an address terminal connected to the address bus and a data terminal connected to the data bus via a second buffer register circuit, and the first storage circuit A first buffer circuit having a data terminal connected to the input and an output connected to the data terminal of the second storage circuit; an output connected to the input of the first buffer circuit; and an input connected to the address bus. A dedicated circuit having a second buffer circuit, wherein a storage write control signal is connected to a control terminal of each of the first and second buffer circuits. A storage read control signal is connected to a control terminal of each of the first and second buffer register circuits, and an address via the second buffer circuit is assigned to an address designated by the data bus of the first storage circuit. The first storage circuit reads data at an address designated by the data bus, and stores the read data in the second data.
To the address specified by the address bus via the second buffer circuit, and stores the value of the address bus before the value of the data bus having the same value into the address designated by the second buffer circuit.
A data search device, wherein the data is stored in a storage circuit.