JPH02230463A - Memory searching circuit - Google Patents

Abstract

PURPOSE:To retrieve data at a high speed by comparing the output data on a memory obtained by inputting the output of a counter into a memory as an address and then into a reading I/O port of a CPU with the writing I/O data of the CPU and using this result as the counter control signal. CONSTITUTION:A memory 1 is prepared together with a CPU 6, a counter 4, and a comparator 2. The counter 4 inputs the addresses which are successively increased to the memory 1 and at the same time gives the set data to a reading I/O port of the CPU 6. The comparator 2 compares the data read out of an address of the memory 1 given from the counter 4 with the data received from the CPU 6 via a writing I/O port. Then the value of the counter 4 is increased until the coincidence is obtained between both data. Thus the data retrieving time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of industrial application) The present invention relates to an improvement in a processor system, and in particular to an Ij P
This invention relates to a system for searching data on memory using U.

(Prior art) Conventionally, when C1'U checked the data on the memory, it read all the memory data each time and compared the conditions while increasing the memory address on the program. .

(Problem that the invention seeks to solve) The conventional data search method described above has the disadvantage that the processing time is extremely long because the memory address setting and data ratio V. are performed on the program. be.

The purpose of the present invention is to input the output of the counter as an address to all the memories and also input it to the read I/O port of the OPTJ, and to combine the output data of the memory and the C! P
Compare the I/O data of U and compare the result of step 7 with the control key number of the full-power counter to eliminate all the above defects,
The purpose is to provide a complete memory search circuit configured to reduce processing time.

(Means for Solving the Problem) The memory search circuit according to the present invention has a memory and a CPU.
and. It is configured with a counter and a comparator.

Memory has multiple addresses and is used to store data.

The CPU is for searching the memo IJy.

Is the counter an address that is sequentially incremented into memory? It is used to input all the setting data to the read I/O boat of the OPU as well as to manually edit the data.

The comparator compares the data read from the address given by the memory counter with the data given from the CPU by opening all write I/O ports, and increases the counter value until both data match. It is for incrementing.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a memory search circuit according to the present invention.

In FIG. 1, 1 is a memory, 2 is a comparator, 3 is a write J/O port, 4 is a counter, 5 is a read I/O port, and 6 is a CPU. Further, 7 to 14 are signal lines, respectively.

Memory 1 has the address OO 0 0-FFI;"F and has an answer size of 256K.

Signal line 7 carries all the output data (8 bits) of memory 1,
Data (8 bits) latched by signal line 8/0 port 3 is loaded.

The signal line 9 carries the write data written by the OPU 6, and the Shingetsu line 10 carries the data on the signal line 7 and the signal line 8.
An interrupt signal to the CPU 6 that is turned on when the above data matches is placed. The signal line 11 carries a strobe signal for writing data to the write I/O port 3.

The strobe signal on the signal line 11 is also an initialization signal for the counter 4. The signal line 12 acts as an address bus for the memory 1 and a data bus for the starting J/0 board 5, and carries the address given to the memory 1 from the counter 4 and the setting data for OPU a. I'll ride it. Signal line 1
3 carries an enable signal used when all data is read from the output port 5/0. Signal line 14 is CP
It acts as a data bus for U6, and carries data input from signal line 12 to OPU6 by an enable signal on signal line l3.

O P U 6 is the data on memory 1” A A (
16) The procedure for searching will be explained below.

When data "AA" is written to the write I/O boat 3 by the CPU 6, "AA" is set to the input signal line 8 of the comparator 2, and the output signal line 12 of the counter 4 is set to "o o".
It is cleared to "o o".

In the memory 1, the data at address "o o o o" is output on the comparator 20 input signal 7. Data is “A”
A'', the comparison result output from comparator 2 on signal line 10 is turned off.

If the comparison result on signal line 10 is not on, counter 4
Is it the output value? Increment and make "O O 0 1" the address of memory 1.

Hereinafter, in the same way, the setting data of OPU 6 "AA"
The memory address is incremented until ``1-'' and the output data of memory 1 match, and when the comparison result on signal line 10 turns on, the increment of the address of memory 1 stops.

At this time, the interrupt for (! ” can be obtained from the memory address where it is stored.

(Effects of the Invention) As explained above, the present invention inputs the output of the counter as an address to all memories and also inputs it to the start I/O boat of (E }' U, and stores the resulting memory. Compare the output data and the OPU write I/O data,
By combining the result with the counter control signal, there is an effect that data retrieval speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a memory search circuit according to the present invention. ■...Memory 2...Comparator 3...Write ■/0 boat 4...Counter 5...Read I/
O boat 6...C'. PU7~14...Signal line

Claims (1)

[Claims] A memory having a plurality of addresses for storing data, a CPU for searching the memory, and inputting sequentially incremented addresses to the memory and setting them to read I/O ports of the CPU. A counter for giving data compares the data successively read from the address given by the counter of the memory with the data given from the CPU via the write I/O port, and the two data match. A memory search circuit comprising: a comparator for incrementing the value of the counter up to .