JPH09305476A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce tasks that a CPU should perform for data retrieval and shorten a search time. SOLUTION: To search for data, an address signal outputted by an address generating circuit 12 is led to an SRAM 3 by a selector 11 and a data signal outputted by this SRAM 3 is led to a comparing circuit 16 by a distributing circuit 14. Then the comparing circuit 15 masks some bits of a search data signal outputted from a search data register 16 with mask data outputted by a mask register 17, compares the partially masked search data signal and the output data signal of the SRAM 3 with each other, and outputs a coincidence signal to the address generating circuit 12 when they match each other. Then the address generating circuit 12 once inputting the coincidence signal stores the corresponding address signal in a matching address storage register 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly, to a data processing device which realizes a search function equivalent to an associative memory for searching data stored in a RAM and speeds up data search. .

[0002]

2. Description of the Related Art As shown in FIG. 3, a data processing device represented by a computer is a CPU for processing data.
(Central Processing Unit) 1, ROM 2 (Read Only Memory) storing instruction code, and SRAM (Static Random Access Memory) 3 storing data 4 and a data bus 5 which is a data signal path.

In such a data processing device, during data processing, the CPU 1 outputs an address signal storing the instruction code of the ROM 2 to the address bus 4, and the ROM 2 outputs the instruction code in response to the address signal. Output to the data bus 5. Then, the CPU 1 uses the ROM 2
The instruction code output from the device is read, a task is executed based on this instruction code, and various data processing is performed.

When performing data search, the CPU 1
Outputs the address signal of the SRAM 3 in which the data to be searched is stored to the address bus 4, and the SRAM 4 outputs the data corresponding to the address signal to the data bus 5. Then, the CPU 1 reads the data output from the SRAM 3, compares the data, and stores the data search result and the like.

[0005]

However, in the above-described data processing device, the CPU 1 has to read the instruction code for each task, so that when searching for data, each task, that is, the SRAM 3 is performed. It is essential to perform the operation of reading the instruction code from the ROM 2 before the operation of reading the data, the comparison operation of the data, the storage of the comparison operation result, and the like.

Therefore, before reading one address data and storing the search result, as shown in FIG.
OM read cycle, SRAM read cycle, ROM
A time (comparison time) for performing at least 6 cycles of a read cycle, a data comparison cycle, a ROM read cycle and a data storage cycle is required, and the CPU
There is a problem that the operation of No. 1 becomes redundant and the processing time required for data search becomes long. The present invention has been made in view of the above problems, and is a C
It is an object of the present invention to provide a data processing device capable of eliminating the redundant operation of the PU and speeding up the data search.

[0007]

To achieve the above object, the present invention provides an address signal in response to a search control signal in a data processing device in which a CPU is connected to a ROM and a RAM via a data bus and an address bus. Address generating circuit, a selector for selectively outputting the address signal output by the address generating circuit or the address signal of the address bus to the RAM according to the search control signal, and a search data register for storing the search data signal. And whether or not the search data signal output from the search data register and the output signal from the RAM match,
The comparison circuit that outputs a match signal when they match, the distribution circuit that selectively outputs the data signal output from the RAM to the comparison circuit or the data bus in response to the search control signal, and the comparison circuit match A match address storage register is provided for storing the output address signal of the address generation circuit when the signal is output.

Known CPUs, ROMs, RAMs, data buses and address buses can be used.
The CPU is configured to output the search control signal and the search data signal. The address generation circuit is composed of a decoder, etc., and sequentially outputs address signals in a predetermined cycle in response to the search control signal (when the search control signal is enabled), and when the comparison circuit outputs a match signal, the corresponding address is output. The signal is output to the match address storage register. And
This address generation circuit, during the generation period of the address signal,
That is, the search state signal for identifying the search state is C
It is configured to output to a PU or the like.

The selector is composed of a gate circuit and the like,
If the search control signal is disabled, the address signal of the data bus is output to the RAM, and if the search control signal is enabled, the address signal output from the address generation circuit is output to the RAM. The search data register stores search data,
The match address storage register is an address signal input from the address generation circuit when the match signal of the comparison circuit is output.
That is, the address data whose data comparison result matches is stored.

The comparison circuit is an exclusive OR circuit (Exclusiv
Comparing the data signal output from the RAM in response to the address signal with the search data signal output from the search data register, a match signal is output if they match, and a mismatch signal is output if they do not match. Output as a comparison result signal. As the match signal and the mismatch signal (comparison result signal), a flag of several bits is used. In a preferred mode, a mask register storing a mask data signal is connected to the comparison circuit, and a part of the search data signal input to the comparison circuit or a part of the output data signal of the RAM is masked to compare the comparison circuit. Speed up the operation.

In the data processing device according to the present invention, the address generation circuit sequentially outputs the address signals in response to the output of the search control signal, and the address signals pass through the selector to RA.
Input to M, the RAM outputs a data signal corresponding to the address signal, and this data signal is input to the comparison circuit via the distribution circuit. Then, the comparison circuit compares the search data signal output from the search data register with the data signal of the RAM and outputs a match signal when they match, and the address generation circuit matches the corresponding address signal by the output of the match signal. It is output to the address storage register and stored in the match address storage register. Therefore, the number of CPU operations can be reduced, and data search can be speeded up.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a data processing device according to an embodiment of the present invention, FIG. 1 is a block diagram, and FIG. 2 is a timing chart at the time of data search. The same parts as those in FIG. 3 described above are designated by the same reference numerals, and illustration and part of the description are omitted.

In FIG. 1, 11 is an address bus 4 and S.
A selector interposed between the RAM 3 and 12; an address generation circuit 12; a match address storage register 13;
A distribution circuit interposed between the RAM 3 and the data bus 5,
Reference numeral 15 is a comparison circuit, 16 is a search data register, and 17 is a mask register.

The selector 11 includes an address generation circuit 12
Connected in parallel with the address bus 4, and the CP not shown
A search control signal is input from the CPU 1 by connecting to U1.
The selector 11 connects the address bus 4 to the decoder of the SRAM 3 (outputs an address signal) when the search control signal is disabled, and connects the address generation circuit 12 to the decoder of the SRAM 3 when the search control signal is enabled. .

The address generation circuit 12 is connected to the CPU 1, the match address storage register 13 and the comparison circuit 15, receives the search control signal from the CPU 1 and the comparison result signal from the comparison circuit 15, and indicates the operating state to the CPU 1. Outputs the search state signal. This address generation circuit 12
When the search control signal is enabled, the address signal is sequentially output to the selector 11 at a predetermined cycle, and the comparison result signal for these address signals is input from the comparison circuit 15. Then, the address generation circuit 12 outputs a corresponding address signal to the match address storage register 13 if it is a match signal indicating that the comparison result signals match, and whether or not the address signal is being output by the search state signal. I will inform you.

The match address storage register 13 stores the address signal output from the address generation circuit 12. The address signal stored in the match address storage register 13 is read by the CPU 1, and the CPU 1 reads the data stored in the SRAM 3 based on the address signal read from the match address storage register 13.

The distribution circuit 14 has the SRAM 3 on the input side,
The data bus 5 and the comparison circuit 15 are connected to the output side, and
A search control signal is input by connecting to the CPU 1. This distribution circuit 14 uses SR when the search control signal is disabled.
The output data signal of AM3 is output to the data bus 5, and when the search control signal is enabled, the output data signal of SRAM3 is output to the comparison circuit 15.

In the comparison circuit 15, the search data register 16 is connected in parallel with the distribution circuit 14 to input the search data signal, and the mask register 17 is connected to input the mask data signal. The comparison circuit 15 masks a part of the bits of the search data signal input from the search data register 16 with the mask data signal input from the mask register 17, and passes through the partially masked search data signal and the distribution circuit 14. The input output data signal of the SRAM 3 is compared. Then, the comparison circuit 15 outputs a match signal to the address generation circuit 12 when the partially masked search data signal and the output data signal match.

The search data register 16 is connected to the CPU 1 and stores a search data signal output by the CPU 1. The mask register 17 is connected to the CPU 1 and
The mask data signal output by U1 is stored. The mask register 17 can also store fixed mask data (signal) in a fixed manner.

In this embodiment, when performing normal data writing and reading, the CPU 1 outputs a disable search control signal, and the selector 11 outputs the address signal of the address bus 4 to the SRAM 3 and the distribution circuit 14. Is SRAM3
The output data signal of is output to the data bus 5. Therefore, when the CPU 1 outputs an address signal to the address bus 4, this address signal is input to the SRAM 3 and the SRA
M3 outputs the stored data at the corresponding address to the data bus 5. Therefore, the data reading from the SRAM 3 and the data writing can be performed in the same manner as a general data processing device, and normal data processing can be performed.

On the other hand, when performing data search, the CPU 1
Outputs an enable search control signal. Therefore, the address generation circuit 12 sequentially outputs the address signal at a predetermined cycle, the selector 11 outputs the address signal output from the address generation circuit 12 to the SRAM 3, and the data signal output from the SRAM 3 based on the address signal. Is output to the comparison circuit 15 by the distribution circuit 14.

Then, the comparison circuit 14 masks a part of the bits of the search data signal input from the search data register 16 with the mask data signal input from the mask register 17, and distributes the masked search data signal and the partially masked search data signal. The data signal output from the circuit 14 is collated, and if they match, a match signal is output to the address generation circuit 12. When the match signal is input from the comparison circuit 14, the address generation circuit 12 receives the corresponding address signal, that is,
The address of the data whose comparison result matches is output to the match address storage register 13 and stored.

The address generation circuit 12 is an SRAM.
Output of address signals corresponding to all addresses of 3 is completed,
That is, when the search ends, the search end signal is sent to the CPU 1
Output to Therefore, the CPU 1 disables the search control signal, reads the address signal from the match address storage register 13, and reads the matching data signal from the SRAM 3 by the read address signal.

As described above, in the data processing apparatus according to this embodiment, the CPU 1 can perform the data search only by outputting the enable search control signal, and the CPU 1 does not need to execute other tasks in the data search. . Therefore, as shown in FIG. 2, when searching for data, the CPU
After 1 performs one ROM read cycle, CP
U1 does not execute the task, and sequentially reads each address data of SRAM 3 to comparison. That is, as is clear from the comparison of the comparison time of 1 address data, the comparison processing of 1 address data is performed by the CPU.
It consists of an SRAM read cycle that does not depend on 1, a data comparison cycle, and a data storage cycle, and the comparison time for one address data is significantly shorter than that of the conventional example (see FIG. 4) described above.

[0025]

As described above, according to the data processor of the present invention, the address signal output from the address generation circuit based on the search control signal is input to the RAM,
The address signal causes the data signal output from the RAM to be guided to the comparison circuit by the distribution circuit to be compared with the search data signal. If they match, a match signal is output to the address generation circuit and the corresponding address data is stored in the match address storage register. Since the data is stored, it is possible to reduce the tasks to be performed by the CPU when searching for data, and it is possible to shorten the data searching time.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a data processing device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the data processing device.

FIG. 3 is a block diagram of a conventional data processing device.

FIG. 4 is a timing chart showing an operation of the conventional data processing apparatus.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Address Bus 5 Data Bus 11 Selector 12 Address Generation Circuit 13 Match Address Storage Register 14 Distribution Circuit 15 Comparison Circuit 16 Search Data Register 17 Mask Register

Claims (1)

[Claims] 1. A data processing device in which a CPU is connected to a ROM and a RAM by a data bus and an address bus, an address generating circuit for outputting an address signal in response to a search control signal, and the address according to the search control signal. A selector that selectively outputs an address signal output from a generation circuit or an address signal of the address bus to the RAM, a search data register that stores a search data signal, a search data signal output from the search data register, and the RAM. Of the output signals of the RAM are compared with each other, and if they match, a comparison circuit that outputs a coincidence signal and a data signal output from the RAM according to the search control signal are selected to the comparison circuit or the data bus. Of the address generating circuit when the comparing circuit outputs a coincidence signal. Data treatment device, characterized in that it comprises a matching address storage register for storing a force address signal.