JPS63123137A - Address coincidence signal generating system - Google Patents

Abstract

PURPOSE:To minimize a hardware by storing address coincidence information to a memory means and when the access is executed common to a memory and a memory means to the stored address, generating an address coincidence signal. CONSTITUTION:An address is assigned as well as a ROM to store a microprogram, a RAM 2 to store address coincedence signal generating data is provided, the access is executed common the to ROM 1 toward the address, in which the address coincidence signal generating data of a RAM 2 are stored, and then, the address coincidence signal is generated. Thus, by a small quantity of hardware that the RAM 2 is only added to a conventional circuit, the address coincidence signal can be generated which is the signal to detect the address coincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an address match signal generation method, and in particular to a method for generating an address match signal, which is used to generate a microprogram signal for testing and diagnosing a logic device operated under the control of a microprogram using a microprogramming method. An address that generates an address match signal at a predetermined address in the memory that stores -
Regarding the signal generation method.

Conventional technology Conventionally, in this type of address match signal generation method, a register that stores predetermined address information for address match detection is used, and the output of this register is compared with an access address to a memory that stores a microprogram. This was realized by an address match signal detection circuit composed of a comparator.

Such a conventional address match signal detection circuit consists of a register that stores predetermined address information and a comparator that compares the output of this register with the memory access address. The drawback is that the comparator and the comparator require the same bit length as the memory access address, and require a large amount of hardware.

Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks of the conventional method, and an object of the present invention is to provide an address match signal generation method that can generate an address match signal with a small amount of hardware. .

The address match signal generation method according to the present invention is an address match signal generation method that generates an address match signal when an access address to a memory matches a predetermined address, and the address match signal generation method according to the present invention is an address match signal generation method that generates an address match signal when an access address to a memory matches a predetermined address. and storage means for storing address-number information for generating the address match signal, and when the access address to the memory is an address for storing the address-number information of the storage means, the address The present invention is characterized in that a coincidence signal is generated.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention includes a ROM (read only memory) 1 and a RAM (random access memory) 2.
, a register (MIR) 3, a decoder (DEC) 4, a +1 adder 5, a register (MAR) 6, a stack memory (RTA) 7, an adder 8 for ±, and a multiplexer (MPX) 9. , and a trap control circuit 10.

ROM1 stores a microprogram, and RAM2 stores address match signal generation data.

Further, the RAM 2 is connected via a data bus 200 to an arithmetic unit 30 in the illustrated loose logic device operated under the microprogramming method and to other control units (not illustrated). Register 3 stores the microcode that is the output of RoMl, and the decoder 4 creates a microcommand based on the output of register 3.

The +1 adder 5 is connected to the ROM which is the output of the multiplexer 9.
1 and the access address input to the RAM 2, an access address +1 is created, and the register 6 stores the access address +1 created by the +1 adder 5. stack memory 7
stores the access address +1 stored in register 6 as the return address when executing a jump instruction or trap operation. The adder 8 creates a jump address in the relative jump instruction and sends it to the multiplexer 9. The multiplexer 9 is connected to the arithmetic unit 30 and other control units in the logic device via an address bus 100.

The trap control circuit 10 inspects and diagnoses the logic device, and instructs a trap operation based on a command from a service processor (SVP) 50 that monitors the operating state of the logic device.

In FIG. 1, ROM'1 and RAM2 are commonly accessed and read by the output signal 91 of multiplexer 9. This means that if you want to obtain an address match signal at a predetermined address of the microprogram stored in ROM1, the RA
This indicates that it is sufficient to write address match signal generation data to address M2.

An update program for the RAM 2 is stored in the ROMI, and when a predetermined address in the RAM 2 is updated, this update program is executed. When updating RAM2 using the update program, RAM2
The access address to is supplied via the address bus 100, and the update data to this access address in RAM 2 is supplied via the data bus 200.

The data to be loaded onto the address bus 100 and the data bus 200 is stored in advance in a mailbox or the like in the main memory (not shown), and is read out by the update program in the RAM 2 and stored in a register (not shown) in the arithmetic unit 30. When storing the data in a file or the like and executing an update microinstruction in the RAM 2, the data is supplied from the arithmetic unit 30 via the address bus 100 and the data bus 200.

The updated address data of the RAM 2 read onto the address bus 100 is supplied to the multiplexer 9 via the connection line 101, selected by the command signal 92, and accessed to the RAM 2 by the output signal 91.

On the other hand, update data to the RAM2 is supplied to the RAM2 via the connection line 201, and the update data to the RAM2 is supplied to the RAM2 via the connection line 201.
Writing to M2 is instructed.

The instruction to execute the update program in the RAM 2 is realized by the service processor 50 instructing the trap control circuit 10 via the connection line 51.

When you want to update RAM2, under the control of the service processor 50, update the RAM to a mailbox in the main memory.
After writing the update address and update data of 2, the RAM2 update command instructed via the connection line 51 is sent from the trap control circuit 10 via the connection line 12 to the update program for RAM2 stored in the ROMI. The start address information is supplied to the multiplexer 9, selectively output via the connection line 11, and executed by accessing the ROM 1 using the output signal 91.

The service processor 50 issues an instruction to execute the update program in the RAM 2 suddenly when necessary, and interrupts the program that has been running up until now.

When the trap control circuit 10 receives an instruction to execute a program for updating the RAM 2 from the service processor 50, it adjusts the timing, uses the +1 adder 5 to add +1 to the access address of the program currently being executed, and registers 6. The input line 12 is instructed to be stored in the stack memory 7 as a return address through the connection line 11, and the input line 12 to the multiplexer 9 is selected through the connection line 11.

The last execution microinstruction of the RAM2 update program is a return microinstruction, and this execution microinstruction returns the resume address of the program stored in the stack memory 7 that was being executed before the execution of the RAM2 update program. Execution of reading is instructed. Execution of the return microinstruction is realized by outputting the return address data supplied from the stack memory 7 to the multiplexer 9 via the connection line 71 as an output signal 91 using the command signal 92, and accessing the ROM 1 with this return address. Ru.

By executing the update program in RAM2, the address match signal generation data stored in RAM2 is output as an address equal signal (address match signal) 21 when ROMI and the address in RAM2 are accessed.
It is output from AM2. The address equal signal 21 is used as an instruction to stop the execution of a microprogram in a logic device and as a synchronization signal for a logic tracer or synchroscope that observes the hardware state inside the logic device.

In this way, RAM2 is provided which is assigned the same address as ROM1 that stores the microprogram and stores address match signal generation data, and the address where the address match signal generation data of RAM2 is stored is shared with ROM1. By generating an address match signal when accessed, it is possible to generate an address match signal, which is a detection signal for address match = 9-, with a small amount of hardware, such as adding RAM2 to a conventional circuit. can.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, address matching information for generating an address matching signal is stored in a storage means assigned the same address as a memory storing a microprogram, and this address matching information is By generating an address match signal when a stored address is commonly accessed by both the memory and the storage means, the effect is that the address match signal can be generated with a small amount of hardware. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Explanation of symbols of main parts 1...ROM (read only memory) 2...
...RAM (Random Access Memory) 9...
... Multiplexer (MPX) 21 ... Address equal signal 30 ... Arithmetic unit 50 ... Service processor (SVP) 100
...Address bus 200 ...Data bus

Claims (1)

[Claims] An address match signal generation method that generates an address match signal when an access address to the memory matches a predetermined address, the address match signal is allocated in the same way as the memory,
and a storage means for storing address matching information for generating the address matching signal, and generating the address matching signal when the access address to the memory is an address for storing the address matching information of the storage means. An address match signal generation method characterized in that: