JPS5965354A - Priority control system for reception of processing request - Google Patents

Abstract

PURPOSE:To facilitate easy setting and change of priority, by deciding previously and storing the priority in response to combinations of processing requesters and giving priority to the requests other than that given immediately before those requests are generated. CONSTITUTION:Processing requests 0-3 are supplied to an AND 2 via a processing request holding register 1. The output of a decoder 7 is (0) at first, and therefore the data of the register 1 is supplied to a memory 4 after passing directly through the AND 2 to be sent to an ID register 5 in accordance with the prescribed priority. At the same time, an OR circuit 3 delivers (1) to set it to a validity display register 6. Thus the data of the register 5 is validated and sent to a processing part. If a processing request 2 is processed at first for instance, an ID2 is set at (1) by the decoder 7 to close the gate 2 of the request (2). This inhibits the continuity of a specific processing request, and at the same time the priority is set and changed easily just by setting and changing the contents of the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a logic circuit of an information processing-related device, and relates to a control method in a circuit that determines the priority order for accepting multiple processing requests that exist simultaneously. .

(2) Prior art and problems In general, in information processing related equipment, when there are processing requests of equal urgency from multiple places, how to select and accept these requests is determined by the design method of the equipment. It depends on the hardware logic (for example, the numerical order of terminals and connectors).

Also, when adding hardware configurations to create an information processing system, take into account the data transfer speed of the transfer device, the characteristics of the input/output devices under it, the processing speed, etc. to avoid any inconvenience. Also, in order to avoid reducing processing efficiency, connections between devices, connector positions, etc. are determined while taking into consideration the priority level in the case of duplicate processing requests.

On the other hand, after an information processing system has been designed and constructed, changes to the system or addition of input/output devices are often made as the user's workload increases or processing content is added or changed. However, at this time, problems may occur unless the priority order of acceptance of processing requests from other devices is set differently from the original design in the transfer device, input/output control device, or the like.

Conventionally, such cases were often dealt with by changing the connections between devices, etc. In this case, since the contents of the system generation (SG) of the system management program (O8) were affected, it was necessary to re-execute the SG. This has the drawback of requiring a lot of manpower and machine time for the work and confirmation tests.

Furthermore, even with the creation of information processing systems, the priority of accepting multiple processing requests is fixed.
The disadvantage is that there is little flexibility in connecting devices, making it difficult to design an optimal design.

(3) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention enables the priority order of acceptance of multiple processing requests to be freely set, and
The purpose is to provide a circuit system that is easy to change.

(4) Structure and purpose of the invention According to the present invention, as described in the claims, p1 for a plurality of processing requests that exist simultaneously,
In a circuit that selects one of them according to a predetermined priority order, a memory is provided, and information including which processing request to select according to the combination of processing request sources is written in the memory in advance. Then, the information stored in the memory is searched for the processing request to be selected from among the processing requests other than the processing request from the same request source as the processing request accepted immediately before. This is achieved by a claim formula that is characterized by determining the

(5) Embodiment of the invention FIG. 1 is a block diagram of an embodiment of the invention.
ll. A processing request holding register, 2 an AND circuit, 3 an OR circuit, 4 a memory, 5 an ID register, 6 a validity display register, and 7 a decoder.

FIG. 2 shows an example of information stored in the memory 4, where 8 is an address, expressed as a binary number, which is equivalent to the combination of processing requests in FIG. 9 is data, and one of the processing requests 0 to 3 is displayed as a binary number corresponding to each address.

In Fig. 1, for example, when processing requests exist simultaneously in lines 0 to 2 but not in line 5, processing request holding register 1 is set to 1110 (11" is set on the line with the processing request. ) is held and input to each AND circuit 2.

In the initial state after this circuit starts operating, the decoder 7
Since the outputs of are all 0, the data of the processing request holding register appears as is at the output of the AND circuit 2.

A part of the output of the AND circuit 2 enters the OR circuit 3, and since its output is 11, the validity display register 6 receives a voltage of 1.
I is set. This indicates that the data in the ID register 5 is valid.

On the other hand, the other part of the output of the AND circuit 2 enters the memory 4 as address information. The memory 4 has data stored in advance as shown in FIG. Set to 5.

This means that 2 is selected from among the processing requests 0 to 2 that exist at the same time, and the binary data 10 in the ID register 5 is sent to the processing unit along with the display signal 1'' in the validity display register. Be notified.

On the other hand, this binary data 10 is decoded by the decoder 7, and the line of ID=2 becomes 11"vl. This suppresses the output of the corresponding AND circuit 2, so at the next timing, the line with ID=2 becomes 11". Even if a request is made from the processing request line 2, it will not be accepted.

Therefore, it is possible to prevent an inconvenience in which only specific processing requests are accepted in succession and other processing requests are not accepted.

Additionally, in some cases, the cycle time for accepting and accepting requests may be accelerated, allowing the next request to be accepted while an already accepted request is being processed, and the preparatory work necessary for processing the request being performed in advance. , it is possible to improve processing efficiency.

(6) Effects of the invention The priority control method for accepting processing requests due to non-invention is IC
It can be easily realized with a simple configuration by using standardized parts, and it is possible to arbitrarily set the priority order of reception of multiple processing requests that exist simultaneously, depending on the content of information written to the memory provided in the circuit. When constructing an information processing system, it is possible to design a system with a rational equipment configuration without being constrained by conditions unique to the device, which is highly effective.

In addition, when you want to change the priority order of processing requests when adding equipment to an information processing system that is already in operation, you can easily change the priority order of processing requests by simply changing the contents of the memory. Moreover, it can be implemented without affecting the system management program (OS), so the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
This is an example of information written to the memory 4. 1... Processing request holding register, 2... AND circuit,
3... OR circuit, 4... Memory, 5... ID register, 6... Validity display register, 7... Decoder, 8... Address, 9... Data

Claims (1)

[Claims] In a circuit that selects one of multiple processing requests existing at the same time according to a predetermined priority, a memory is provided to determine which processing request is selected depending on the combination of processing request sources. Information is stored in the memory in advance
4# After importing, target the processing request that was accepted immediately before and other processing requests that were accepted from the same request source.
A claim characterized in that a processing request to be selected from among the processing requests is determined by searching information written in the memory.