JP2962209B2 - In-circuit emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an in-circuit emulator, and more particularly to discriminating between a memory space used in a microcomputer and a target memory space and an unused memory space, and executing data in the unused memory space as a program. The present invention relates to an in-circuit emulator having a function of prohibiting the operation.

[0002]

2. Description of the Related Art In general, an in-circuit emulator is a device used to realize an operation function of a specific microcomputer. One of the functions of this in-circuit emulator is a mapping function. Regarding the memory space of the microcomputer to be emulated and the memory space of the entire target system using the microcomputer, the used memory area of the memory space is defined as a mapping area, and the unused memory area is unmapped. Areas are defined and clearly distinguished from each other. The function of detecting access to the non-map area is the above-described mapping function. The mapping function includes a function of stopping the emulation operation function when data in the non-map area is executed as a program. A state in which the emulation operation function is stopped by this function is generally called a non-map break.

FIG. 7 is a block diagram showing a configuration of a conventional in-circuit emulator. As shown in FIG. 7, the in-circuit emulator 14 of the conventional example includes a program memory 2, a mapping memory 3, and a host computer 7 connected to the in-circuit emulator 14 via a cable 201. An I / F unit 4 and an evaluation chip 5 are provided, and a data bus 20 is provided between the program memory 2 and the evaluation chip 5.
And an address bus 203 between the program memory 2, the mapping memory 3 and the evaluation chip 5.
Is connected.

[0004] In FIG. 7, as described above, the in-circuit emulator 14 is connected to the host computer 7 by the cable 201.
Is connected via an I / F unit 4 to an evaluation chip 5 which performs the same operation as that of the microcomputer to be emulated and further realizes some of the functions provided in the in-circuit emulator 14. A data signal 101 required by the host computer 7 is output from the evaluation chip 5 and transmitted to the host computer 7 via the I / F unit 4. In this case, Eva chip 5
Is executed by the evaluation chip 5
Are stored in the program memory 2 connected via the data bus 202 and the address bus 203.

[0005] Data for discriminating between the mapping area and the non-map area is stored in a mapping memory 3, which is connected to the same address bus 203 as the program memory 2. If an address exists in the mapping area, data "1" is written. If the address exists in the non-map area, data "0" is written. The non-map break request signal 105 output from the mapping memory 3 is input to the evaluation chip 5. When the non-map break request signal 105 output from the mapping memory 3 is at the “1” level, the operation of the evaluation chip 5 does not stop the emulation operation function. But,
When the non-map break request signal 105 output from the mapping memory 3 is at the “0” level, the emulation operation function is stopped by the evaluation chip 5 to enter a non-map break state, and the subsequent processing is not continued. Become.

FIG. 9 is a diagram showing a configuration of a program memory 15 for storing a program used in the description of the conventional example. FIGS. 8 (a), 8 (b) and 8 (c) show non- FIG. 6 is a timing chart showing a map break operation. Hereinafter, the non-map break operation in the conventional example will be described with reference to FIGS. 7, 8 and 9. FIG.

First, the instruction “BR! 100” in the mapping area of the program memory 15 is generated by the evaluation chip 5.
H "(see FIG. 8A) is prefetched. At this time, as described above, the non-map break request signal 105 (see FIG. 8C) is set to" 1 "level from the mapping memory 3. And is input to the evaluation chip 5. In the evaluation chip 5, the instruction "BR!
100H "is performed, and at the same time, data at address 2000 in the non-map area of the program memory 15 is prefetched. In this case, the mapping memory 3
Non-map break request signal 105 output from
At timing T ₈ , the signal is output at the “0” level (see FIG. 8B) and input to the evaluation chip 5. In response to this, the command “BR! 100H” issued by Eva Chip 5
At time T ₁₀ run (which see FIG. 8 (c)) is completed, the emulation operation function by the evaluation chip 5 terminate the process is stopped. Thereby, the subsequent processing is stopped.

[0008]

In the conventional in-circuit emulator described above, a non-map break request signal is inevitably generated when pre-fetching the non-map area of the program memory. However, depending on the program memory, the mapping area may be used effectively up to the boundary point between the mapping area and the non-map area. In such a case, the boundary point between the mapping area and the non-map area may be used. Due to the non-map break that occurs in the foreground,
There is a disadvantage that the subsequent processing is stopped and it becomes impossible to continue the predetermined processing.

[0009]

Configuration of the present invention In order to achieve the above object, according a first data storage means for storing the program, the first emulation by executing the program stored in the data storage means the target microcomputer equivalent Information processing means for performing a processing operation; and a second memory for storing data for determining a used memory area used in a memory space of the microcomputer to be emulated and the entire memory space of the target system and an unused memory area not used. and data storage means, by the braking <br/> control of the information processing means receives the determination signals using a memory area / nonuse memory area output from said second data storage means,
If the determination signal is a signal indicating a non-use area, at least a emulation function control means for generating and outputting an emulation stop request signal to the information processing unit, a host information processing means connected to an external In-circuit emulator that operates in response to
The emulation function control means is constituted by a pseudo prefetch buffer having the same function as a prefetch buffer included in the information processing means, and the discrimination signal from the second data storage means indicates a non-use area. If it is, the sync control signal output from the information processing unit, and outputs to generate an emulation stop request signal.

[0010]

The emulation function control means inputs the discrimination signal from the second data storage means and the least significant bit of an address signal output from the information processing means. wherein an output of the logical OR operation, the output and which ANDs inputs an output signal obtained by inverting the determination signal and the least significant bit of the address signal Te et
It may be made up of a circuit serving as a simulation stop request signal .

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, the in-circuit emulator 1 of the present embodiment includes a program memory 2 corresponding to a host computer 7 connected to the in-circuit emulator 1 via a cable 201;
Mapping memory 3, I / F unit 4, and evaluation chip 5
And a pseudo prefetch buffer 6. A data bus 202 is connected between the program memory 2 and the evaluation chip 5 as in the conventional example, and the program memory 2, the mapping memory 3 and the evaluation chip 5, an address bus 203 is connected.

1, the in-circuit emulator 1 is connected to the host computer 7 via a cable 201 in the same manner as in the conventional example. An evaluation chip 5 which performs the same operation as the computer and further realizes a part of the functions provided in the in-circuit emulator 14 is connected. A data signal 101 required by the host computer 7 is output from the evaluation chip 5 and transmitted to the host computer 7 via the I / F unit 4. The program executed in the evaluation chip 5 is stored in the program memory 2 connected via the data bus 202 and the address bus 203. Data for discriminating between the mapping area and the non-map area is stored in the mapping memory 3. If a certain address exists in the mapping area, data "1" is written, and the data in the non-map area is written. , The data “0” has been written. The non-map break request signal 105 output from the mapping memory 3 acts as a non-map break request signal for the evaluation chip 5, and when the level is "1", the emulation operation function of the evaluation chip 5 is activated. When the level is "0", the emulation operation function is stopped. In the present embodiment, the signal 105 is not directly input to the evaluation chip 5, but is input to the pseudo prefetch buffer 6 via the control signal 102 output from the evaluation chip 5.

FIGS. 2A, 2B and 2C are diagrams showing the configuration and operation of the pseudo prefetch buffer 6. FIG. The non-map break request signal 105 input from the mapping memory 3 is controlled by the control signals 102/103/104 output from the evaluation chip 5, input to the pseudo prefetch buffer 6, and output as the control signal 106. It is input to the evaluation chip 5.
Here, the control signal 102 is a “prefetch buffer read signal” for outputting data from the pseudo prefetch buffer 6, and the control signal 103 is the last signal of the pseudo prefetch buffer 6 based on the prefetch buffer read signal. This is a "prefetch buffer / write signal" for newly taking data in the foremost stage of the pseudo prefetch buffer 6 in response to the output of the stage data. The control signal 104 is a “prefetch buffer / flash clear signal” for clearing all data in the pseudo prefetch buffer 6.

That is, in response to the output of the non-map break request signal 105 output from the mapping memory 3,
When the control signal 102 is input to the pseudo prefetch buffer 6, the control is performed by the control signal 102,
The data of the last stage of the pseudo prefetch buffer 6 is output as the control signal 106 and sent to the evaluation chip 5, and at the same time, in the pseudo prefetch buffer 6, the data of the preceding stage advances by one stage. And control signal 1
When 03 is input, the data is input to the foremost stage of the pseudo prefetch buffer 6 under the control of the control signal 103, and the data of the subsequent stages advance one by one. Finally, upon receiving the control signal 104, all the data in the pseudo prefetch buffer 6 is cleared. These control signals 102/103/104 are
This signal is equivalent to a signal for operating the prefetch buffer 6 itself. The non-map break request signal 105 output from the mapping memory 3 is the control signal 102 /
Through the control action of 103/104, the pseudo prefetch memory 6 operates in synchronization with the instruction read from the program memory 2, and at the time when the instruction is executed, the pseudo prefetch buffer 6 outputs the control signal 106 as the control signal 106. It is output and input to the evaluation chip 5.

FIGS. 3 (a), 3 (b), 3 (c), 3 (d),
(E), (f), and (g) are timing charts showing a non-map break operation at the time of program execution of the present embodiment. In this case, the program executed in the present embodiment uses the same program as that of the program memory 15 used in the conventional example shown in FIG. Hereinafter, the non-map break operation according to the present embodiment will be described with reference to FIGS. 1, 2, 3, and 9. FIG.

First, the instruction "BR! 100H" in the mapping area of the program memory 15 shown in FIG. 9 is prefetched by the evaluation chip 5 (FIG. 3).
(A)). In the pseudo prefetch buffer 6, at timing T ₁ , controlled by the control signal 102 input from the evaluation chip 5, the “1” level non-map break request signal 105 output from the mapping memory 3 (FIG. 3C) 3), and is controlled by the control signal 103 to output a control signal 106 of “1” level (see FIG. 3D), which is sent to the evaluation chip 5. In the evaluation chip 5, the prefetched instruction "BR! 100H" is executed (see FIG. 3B), and at the same time, the data at the address 2000 in the non-map area of the program memory 15 (see FIG. 9) is prefetched. (See FIG. 3A). In this case, a non-map break request signal 105 outputted from the mapping memory 3, at timing T ₂ "0"
Level (see FIG. 3 (c)).
_{At 3} , it is controlled by the control signal 103 and input to the pseudo prefetch buffer 6 (see FIG. 3F). In the evaluation chip 9, the control signal 104 is output when the execution of the instruction “BR! 100H” is completed,
At timing T ₄ , in response to the input of the control signal 104, all data in the pseudo prefetch buffer 6 is cleared. And after that, the next instruction,
For example, the processing shifts to the fetch operation of the instruction at the address 100 shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 4, the in-circuit emulator 8 of the present embodiment corresponds to the host computer 7 connected to the in-circuit emulator 1 via the cable 201, and stores the program memory 2
, A mapping memory 3, an I / F unit 4, an evaluation chip 9, and a break tag generation unit 10, as in the conventional example and the first embodiment. The data bus 2 is connected to the evaluation chip 9.
02 is connected between the program memory 2, the mapping memory 3 and the evaluation chip 9.
3 are connected.

As in the case of the conventional example and the first embodiment, in FIG.
The host computer 7 is connected to the host computer 7 via a cable 201. The cable 201 performs the same operation as the microcomputer to be emulated via the I / F unit 4, and further includes one of the functions provided in the in-circuit emulator 8. The evaluation chip 9 that realizes the unit is connected. From the evaluation chip 9, the host computer 7
Output the required data signal 101,
The data is sent to the host computer 7 via the I / F unit 4. The program executed in the evaluation chip 9 is stored in the program memory 2 connected via the data bus 202 and the address bus 203. Further, data for discriminating between the mapping area and the non-map area is stored in the mapping memory 3.
When a certain address exists in the mapping area, data “1” is written, and when it exists in the non-map area, data “0” is written. As described above, the non-map break request signal 105 output from the mapping memory 3 acts as a non-map break request for the evaluation chip 5, and when the level is "1", the emulation operation function of the evaluation chip 9 The emulation operation function is stopped when the operation state is set to "0" level. In the present embodiment, the non-map break request signal 105 is
The input is not directly input to the evaluation chip 9, but is input to the break tag generation unit 10 via the fetch address least significant bit signal 107 output from the evaluation chip 9.

FIG. 5 is a circuit diagram showing a configuration of the break tag generation unit 10, which is configured as a logic circuit including a NOR circuit 11, an inverter 12, and an AND circuit 13. In FIG. 5, a non-map break request signal 105 output from the mapping memory 3 and a fetch address least significant bit signal 10 output from the evaluation chip 9 are shown.
In response to the input of 7, a break request signal 108 _L and a break request signal 108 _H are output from the break tag generation unit 10 and input to the evaluation chip 9. Note that these break request signals are usually called break tags. The break request signal 108 _L is a break tag that synchronizes with data at an even address inside the evaluation chip 9, and the break request signal 108 _H is
Is a break tag that synchronizes with the data of the odd number address inside the. These break tags are at the “1” level when active, indicating that a break is requested. In FIG. 5, the non-map break request signal 105 output from the mapping memory 3 is "0".
When the fetch address least significant bit signal 107 output from the evaluation chip 5 is also at the “0” level, the break request signal 108 _L is output as the “1” level, and the non-map break request signal 105 is output at the “1” level. When the fetch address least significant bit signal 107 is at “1” level at “0” level, the break request signal 1
08 _H is output as "1" level.

FIGS. 6 (a), (b), (c) and (d)
FIG. 6 is a timing chart showing a non-map break operation at the time of executing a program according to the present embodiment. Also in this case, as in the first embodiment, the program executed in the present embodiment uses the same program as that used in the conventional example shown in FIG. In the following, referring to FIGS. 4, 5, 6 and 9,
The non-map break operation according to the present embodiment will be described.

First, the instruction "BR! 100H" in the mapping area of the program memory 15 (see FIG. 9) shown in FIG. 9 is prefetched by the evaluation chip 9 (see FIG. 6A). The non-map break request signal 105 is output at the “1” level from the mapping memory 3 and is input to the break tag generator 10 (FIG. 6C).
reference). The break request signal 108 is output from the break tag generation unit 10 at the “0” level (FIG. 6).
(D)). In the evaluation chip 9, the prefetched instruction "BR! 100H" is executed (FIG. 3).
At the same time, data at address 2000 in the non-map area of the program memory 15 (see FIG. 9) is prefetched (see FIG. 3A). In this case,
The non-map break request signal 105 output from the mapping memory 3 is output at the “0” level (see FIG. 3C) and input to the break tag generator 10. Then, at the timing T ₆ , the break request signal 108 is “1” from the break tag generator 10.
It is output at the level and input to the evaluation chip 9. Then, when the execution of the instruction “BR! 100H” by the evaluation chip 9 is completed, the break request signal 108 captured in the evaluation chip 5 is cleared, and thereafter, the next instruction, for example, as shown in FIG. 10
The operation shifts to the fetch operation of the instruction at address 0.

That is, in the present invention, the non-map break request signal output by discriminating the mapping area and the non-match area output from the mapping memory 3 is transmitted to the evaluation chip via the pseudo prefetch buffer or the break tag generation circuit. In this way, it is possible to prevent the occurrence of a non-map break failure immediately before the boundary between the matching area and the non-map area in the program memory. All areas can be used effectively.

[0025]

As described above, according to the present invention, a non-map break request signal for identifying a mapping area and a non-match area output from a mapping memory is provided.
By inputting the data to the evaluation chip via a pseudo prefetch buffer having the same function as the prefetch buffer in the evaluation chip or the break tag generator operating in synchronization with the fetch address without directly inputting the data to the evaluation chip, the matching area between the program memory It is possible to prevent the occurrence of a non-map break just before the boundary with the map area, and to effectively use the area of the mapping area in the program memory when executing the program. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of a pseudo prefetch buffer according to the first embodiment.

FIG. 3 is a timing chart of a non-map break operation in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a break tag generation unit according to a second embodiment.

FIG. 6 is a timing chart of a non-map break operation in the second embodiment.

FIG. 7 is a blog diagram showing a conventional example.

FIG. 8 is a timing chart of a non-map break operation in a conventional example.

FIG. 9 is a configuration diagram of an example of a program memory.

[Description of Signs] 1, 8, 14 In-Circuit Emulator 2, 15 Program Memory 3 Mapping Memory 4 I / F Unit 5, 9 Evaluating Chip 6 Pseudo Prefetch Buffer 7 Host Computer 10 Break Tag Generator 11 NOR Circuit 12 Inverter 13 NAND circuit 101 Data signal 102 to 104, 106 Control signal 105 Non-map break request signal 107 Fetch address least significant bit signal 108, 108 _L , 108 _H Break request signal 201 Cable 202 Data bus 203 Address bus

Claims (2)

(57) [Claims] 1. A information to be a first data storage means for storing a program, the microcomputer processing equivalent operation of emulated running program <br/> beam stored in the first data storage means Processing means, and second data storage means for storing data for determining a used memory area used in a memory space of the microcomputer to be emulated and the entire target system and an unused memory area not used,
The control of the information processing unit, when the use is output from the second data storage means inputs the determination signal of the memory area / nonuse memory area, the discrimination signal is a signal indicating the unused area, the At least a emulation function control means for generating and outputting an emulation stop request signal to the information processing unit, it operates in response to the host information processing means connected to the external-circuit
In the emulator, the emulation function control means is constituted by a pseudo prefetch buffer having the same function as a prefetch buffer included in the information processing means, and the determination signal from the second data storage means determines an unused area. when a signal indicating, in-circuit emulator, characterized in that the synchronous control signal outputted from said information processing means, and generates and outputs an emulation stop request signal. 2. A first data storage means for storing the program, performs the same processing operation and emulated microcomputer running program <br/> beam stored in the first data storage means Information processing means, and second data storage means for storing data for determining a used memory area used in a memory space of the microcomputer to be emulated and the entire target system and an unused memory area not used; ,
The control of the information processing unit, when the use is output from the second data storage means inputs the determination signal of the memory area / nonuse memory area, the discrimination signal is a signal indicating the unused area, the At least a emulation function control means for generating and outputting an emulation stop request signal to the information processing unit, it operates in response to the host information processing means connected to the external-circuit
In preparative emulator said emulation control means, and arithmetic logic sum inputs the least significant bit of the determination signal and the address signal outputted from the information processing unit from said second data storage means output And an output obtained by inverting the discrimination signal.
Signal ANDed with the output and the emulation stop request signal to input the least significant bit of the address signal
An in-circuit emulator characterized by comprising a circuit as a signal .