JPS622317A - Multilevel comparison and coincidence detecting circuit - Google Patents

Abstract

PURPOSE:To detect a coincidence compactly and with a high function even in case of a data having a wide bit width, by dividing an input data and supplying them as the respective addresses to plural memories, and detecting a coincidence of pattern data which is read out of each memory. CONSTITUTION:First of all, a compared value data A2 is selected by a selecting signal 6, divided into 8 bits each and outputted as an address of each memory 7-9 through an output line 5. 4 bits of a coincidence detecting pattern data 4 are given to the respective data IN of each memory 7-9, and are written in each memory 7-9 by using an address which is divided by a write permitting signal 13. In this state, a selector is switched by the signal 6 and an input data B3 is outputted onto a line 5, and by its divided address, a data is read out of each memory 7-9. In case the data A2 coincides with the data B3, the addresses of each memory 7-9 coincide, as well, therefore, the same pattern data which is written can be read out. Its coincidence is confirmed by a comparing circuit 14 and a coincidence output 15 is outputted.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to data comparison and number composition, and in particular to comparison of data with a wide bit width (large bit length) - multi-value comparison matching suitable for number composition. Regarding a detection circuit.

[Technical background of the invention]

Conventionally, to compare data, a comparator is used to detect a match. At this time, in order to compare a plurality of values, a method has been adopted in which a plurality of registers for comparing input data and a plurality of comparators are paired with the registers.

[Problems with background technology]

In order to compare one value, a register storing a comparison value and a comparator form a pair, and in order to compare a plurality of values at the same time, the number of circuits mentioned above is required. Therefore, the conventional technology has a problem in that the bit width is wide and a large number of circuits are required to detect coincidence by multi-value comparison. Furthermore, in order to simplify the circuit, a single comparator must be used to compare a plurality of components, which takes a lot of time.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to improve the above-mentioned conventional problems, it is an object of the present invention to provide a multi-value comparison coincidence detection circuit that can efficiently compare multi-value data having a wide bit width.

[Summary of the invention]

The present invention includes a plurality of memories, a comparison circuit that compares the output data of the memories bit by bit to detect a match, and selects one of the plurality of data to be compared having a wide bit width.
It is equipped with a data selector or a data bus that divides the data according to the capacity of each memory and inputs the data as the address input of each memory. If pattern data is input and the input data is switched by the data selector and the input data is the same as the previous data, the comparison circuit detects a match by outputting the same match detection data from each memory. , it is possible to perform compact and highly functional match detection even for data with a wide bit width.

[Embodiments of the invention]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the comparison circuit example shown in the figure and its peripheral circuit operation;

In these figures, the data selector switches between A input and B input and outputs the data. (2 is the A input, which is one of the comparison values, and ■ is the input data, which is the other one of the comparison values.)
is the pattern data input that mediates match detection, ■ is the line of data selected by selector ■, ■ is selector ■
This is the selection signal. (7), (8), and (9) are memories, respectively, to which an address is supplied via the output line (2), and the pattern data input (A) becomes the write data.
(10) (11) (12) are each memory ■～■
(13) is a write permission signal for each memory (1) to (2), (14) is a comparison circuit, and (15) is a coincidence output. (21) (22) (23) (24) shown in Figure 2
) and (25) are AND circuits.

Next, an example of operation will be explained. FIG. 1 shows a circuit configuration for comparing 24-bit parallel data (1) and (2) via 4-bit pattern data (A) and detecting a match. First, the comparison value input data A■ is selected by the selection signal 0, and the 24-bit data is divided into 8 bits each according to the capacity of each memory ■~■ and sent to each memory ■~■ via the output line ■. ) is output as the address. - The 4 bits of the pattern data (a) for number configuration are given to the data IN of each memory ~0, and the divided addresses are used by the write permission signal (13) to write each memory ~~0. ) is written.

In the above state, the selector is switched by the selection signal (2) to output the input data B (2) to the outer line (2), and data is read from each of the memories (1) to (2) using the divided addresses. If the input data A2 matches the input data BC3, the addresses to the memories (2) to (9) also match, so that the same written pattern data can be read out. The match is confirmed by the comparator circuit (14) and a match output (15) is output. That is.

The comparison circuit (14) is an AND circuit (2) as shown in FIG.
If all of 1) to (24) are true, and the AND of these outputs is also true, a coincidence output (15), for example, II I
II is output. If there is a difference between input data A■ and input data B■, the read data from memory ■~0, which is given an address different from the write address, is different and 110'' is output as the match output (15), so there is a mismatch. It can be seen that the comparison circuit (14) is not limited to the example shown in FIG.
) to (24) are output separately,
When this is detected, if there is a mismatch, the input data A■, B■
You can also find out which part of your throat is having problems.

Although the above description has simply been about comparing and detecting a match between a plurality of data having multiple values, the present invention can also be utilized for specific character detection in transmission, match detection in a search function of arithmetic operations, and the like.

〔Effect of the invention〕

The present invention is as described above, and has the effect of enabling compact and highly functional match detection even for data with a wide bit width.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of the comparison circuit shown in the figure and its operation. . 1; Data selector, 2, 3; Two comparison data, 4; - Pattern data for number structure, ? ,8,9
;Memory, 10.11,12:Memory output,
14; Comparison circuit.

Claims (1)

[Claims] A data selector into which two bit-width comparison data are input, the data selected by this data selector is divided into multiple pieces, each data is supplied as its own address, and pattern data for match detection is supplied as write data. A multi-value comparison match detection circuit comprising: a plurality of memories; and a comparison circuit that detects a match between the pattern data read from each of the memories.