JPS62106526A - Reading method for input signal - Google Patents

Abstract

PURPOSE:To read an input signal containing plural parallel bits accurately and in a short time by carrying out simultaneously both OR and AND arithmetic operations of corresponding bits of each input signal with these bit set in parallel and changing the flag corresponding to the input signal according to the results of said arithmetic operations. CONSTITUTION:A processing circuit 1 contains P0, P1-P7 which are connected to a processing means 2 via A/D converters C0, C1-C7. The circuit 1 also includes a port register R which stores temporarily the sampled value, accumulators A and B, memories M1 and M2, a work memory W for arithmetic operations, and a flag register F which stores the input signals read from the results of arithmetic operations using them for subsequent arithmetic operations. These register R, accumulators A and B, memories M1, M2 and W, and register F have 8-bit store cells in response to those terminals P0-P7 to which the bits of the input signal are supplied.

Description

Description: TECHNICAL FIELD The present invention relates to a method for reading an input signal consisting of a plurality of bits in an 11 mil column using a micro combinator or the like.

? When reading input signals input to a micro combinator or the like, it is necessary to read them accurately regardless of noise such as chattering. As shown in FIG. 3, the typical prior art requires a long processing time to read an input signal consisting of a total of 8 bits (1st to 7th bits) in parallel. Step r1
Then, the process moves to step r2, and a total of 8 bits of input signals are read into the port recorder R2, and the contents are stored in the accumulator A. The contents of this accumulator are
It is transferred to another 7 storage unit B in step r3. Steps r4 to 13 are operations for determining the logical value of the lowest O-th bit of the human input signal.As the 0-th bit, first, the waveform shown in Figure 4 (]) is derived from the signal source. Assume that the waveform shown in FIG. 4 (2) is input due to chattering.In step r4, accumulator A and the lowest 0th bit are logic rlJ, and the remaining 1st to 7th bits are logic The logical product AND with the hexadecimal number "00000001J (abbreviated with reference mark 01H)" which is "0" is calculated, and the existence of accumulator A is changed. In step "5, it is determined whether the 0th bit is logic [01]. However, if not, that is, if the logic is "1", the contents of the memory MO are incremented by 1 and non-incremented. The contents of the memory MO are shown in FIG. 4(3). In this way, in step r7, 7 mol) M
When it is determined at tII that the value of O is greater than or equal to a predetermined constant value, the constant value is stored in the memory hi at input step r8.
Store in O. In step r9, the 0th bit is 7.
The lag is set as shown in FIG. 4 (4), and the ptS0 bit is thus read as being logical rlJ.

When the 0th bit is logic 0 in step 5, the process moves to step riO, and the memory MO is decremented by 1. As a result, when the contents of the memory MO become less than or equal to zero in step rl I , zero is stored in the memory MO in step r12.

At step r+3, the flag of the 0th bit is reset. In this way, the Oth pin V is read as being logic [04].

In step 14, the contents of accumulator B are transferred to accumulator A. In step r15, the same operations as in steps 4 to r13 for the O-th bit are performed sequentially for the remaining 1st to 7th bits. Then, the process ends at r16.

Problems to be Solved by the Invention In such prior art, the content of each sampled bit is capped by a constant i1α in step r7 or zero in step rll, thereby making each bit a logic "1". is or logical r
OJ is read, and a total of 8 such operations are performed.
This is done sequentially for Pitsu Y. Therefore, it takes a long time each time to read an input signal, which is a big problem when quick processing is required.

An object of the present invention is to accurately input an input signal consisting of multiple bits in parallel, regardless of noise such as chattering.
Moreover, the purpose is to provide a method for reading in a short time.

Means for Solving the Problems The present invention samples each input signal consisting of a plurality of parallel bits multiple times at time intervals and stores the samples.
Step 1 is to perform the OR and AND operations of the corresponding bits of each input signal sampled multiple times on the +E column all at once, and change the flag corresponding to the input signal based on the operation result. This is a method for reading input signals.

Effects of the present invention (input consisting of a plurality of bits in parallel (inputs consisting of multiple bits in parallel) are sampled and stored several times, and based on the stored contents, the corresponding bits for each sampling are stored. Since we performed the logical sum and logical product operations in bit parallel at the same time and read the operation results, r
Compared to the method of sequentially performing operations for each bit in the prior art described in connection with FIGS. 3 and 4 above, the time required for reading can be significantly shortened.

heavenly example FIG. 1 is a block diagram of one embodiment of the present invention.

The processing circuit 11 realized by a microcomputer/computer etc. has input terminals PO, PI, . . . , P7, which perform analog/dinotal conversion WXCO, CI, .
.

The signal is input to the processing means 2 via C7. This processing circuit 1
is a boat renos = PR that temporarily stores the gambling value, and an accumulator A.

B, memories Ml and M2, a work memory W used for arithmetic operations, and a ν/7 lag register F for storing the input signal read as a result of the arithmetic operation and using it for subsequent arithmetic operations.
including. These Renosph R1 accumulators A, B
, memories Ml, M2. W and Renostar F each have 8-bit store cells corresponding to input terminals PO to P7 to which each bit of the input signal is input.

The input signal reading operation will be explained with reference to FIG.

Moving from step n1 to step n2, the input terminal PO-
A total of 8 bits of input signals input to P7 are sampled and stored in the boat renostar R, and the contents are first transferred to the accumulator A. In step n3, the contents of the accumulator are transferred to the 7 accumulator B.

In step n4, the contents of the accumulator A and the contents of the memory M1 that stores the value of the input number sampled for the number of times are ANDed, and the result of the operation is stored back into the seventh accumulator. Then step 115
Then, the logical product AN of the contents of accumulator A and the contents of memory M2 that stores the value of the input signal sampled last time is calculated.
D is calculated and the result is transferred to work 7 and W. Step n4. The logical AND operation in n5 is performed for each bit at the same time.

As a result, immediately before performing the operation in step n4, and 7+
Only when the contents of each bit of the memory unit A and the contents of the corresponding bits of the memories M1 and M2 are all logic "1", the corresponding bit of the work memory W becomes logic "1".
The stored contents of accumulator A immediately before the operation in step n4 and the memory M1. When at least one of each corresponding bit with the stored contents of M2 is a logic "0", the corresponding bit of the work memory W is stored as a logic "0".

In step n6, the contents of accumulator B are transferred to accumulator A. In the step lower, the contents of accumulator A and the contents of memory M1 are ORed for each bit, and the result of the operation is
Stored in At step n8, the contents of the accumulator and the contents of memory M2 are logically ORed, and the result is stored in accumulator A.

In this way, the contents stored in the accumulator A and the memory M1 . All three bits corresponding to the store contents of M2 are logic "0"
When , the corresponding bit of accumulator A in the operation result of step n8 will be stored as logic "0". When at least one of the corresponding bits of accumulator A and memories M1 and M2 immediately before the operation in step n7 is logic "1", as a result of the operation in step n8, the corresponding bit of accumulator A is logic "1". ”.

7 cumulator A as a result of the operation in step n8
The stored contents are as shown in Table 1, for example.

(Left space below) Table 1 In step n9, the logical AND operation of the contents of accumulator A and the contents of 7-lag nosta F is performed,
The calculation result is stored in the 7th storage unit A. Assuming that the contents stored in flag register F at the time of step 1]9 are shown in Table 1, the contents stored in accumulator A as a result of the operation in step n9 are also shown in Table 1. becomes. Further, in step 1 10, a logical sum OR operation is performed for each bit of the contents stored in the accumulator and the contents stored in the work memory W, and the result is stored in the 7-puffer register F as shown in Table 1.

In step nil, the contents of memory M1 are changed to memory M
At step n12, the contents of the 7 storage unit B are transferred to the memory 17M1, and preparation for the next operation is performed. At step n13, the series of processing ends.

The operation of steps 01 to n13 is approximately 10'', for example.

Based on the results of AND and OR operations performed in SQQ, accumulator A stores the current sampling contents, memory M1 stores the previous sampling contents, and memory M2 stores the +'++f times' contents. , these accumulators A, memory Ml
, M2 have the same logical value, the corresponding bits of flag register F are rewritten and updated, and these seven cumulators A and memories M1 . When at least one logical value of the corresponding bit of M2 is different, the contents of the corresponding bit of flag register F are maintained as they are. Therefore, only when each bit of the input signal has the same logical value for at least twice the time interval 10+esec associated with sampling, that is, 20m5ec,
Update the contents of the corresponding bit in that flag register,
Otherwise, the contents of F in the flag register are left unchanged. In this way, the result of reading the input signal is prevented from being erroneously caused by short-lasting noise such as chattering.

In another embodiment of the invention, in the embodiment described above, the memory M
Although a total of two I and M2 are provided, as an embodiment of the present invention, a plurality of ponds are used, and the read result is updated only when the logical value of each bit of the input signal at each sampling lasts for a longer period of time. In this way, the filtering effect may be improved.

Effects As described above, according to the present invention, a bit is set to logic "1" only when the logic "1" of the bit of the input signal consisting of a plurality of parallel bits continues to be "1" by the AND operation by sampling. , and only when the logical "0" state of a bit continues due to the operation of logical sum OR, that bit is read as logical rOJ, and such K of each bit is
Since n is performed in parallel, it is possible to perform the reading process quickly. This can be implemented particularly advantageously in microcomputers, etc., which have a large number of inputs and therefore a large number of bits.

[Brief explanation of drawings]

The fpH diagram is a block diagram of one embodiment of the present invention, FIG. 2 is a 70-chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a 70-chart for explaining the prior art. - Chart, FIG. 4 is a waveform diagram for explaining the prior art which is similar to FIG. 3. DESCRIPTION OF SYMBOLS 1... Processing circuit, 2... Processing means, R... Boat renostar, A, I3... Accumulator, Ml, M2
...Memory, W...Work memory, F...Flag register, PO~P7...Input terminal, Co-C7...
・Analog/Anotal Converter Agent Patent Attorney Keiichi Saikyo Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] Each input signal consisting of multiple parallel bits is sampled multiple times at time intervals and stored, and the logical sum and logical product operations of the corresponding bits of each input signal sampled multiple times are performed simultaneously in bit parallel. A method for reading an input signal, characterized in that a flag corresponding to the input signal is changed according to the result of the calculation.