JPS62237552A - Test address control system - Google Patents

Abstract

PURPOSE:To change a range without changing wiring by providing a non- operation address storing register for optionally setting up an output of a test address register on the basis of a non-operation address control signal inputted from the external. CONSTITUTION:A range setting up '1' in the bits of an operation range address register 1 is a part setting up '0' in an operation address digit part or a non- operation address digit part. An address calculating circuit 3 calculates the operation range address digit part on the basis of an address control signal obtained from a control storage 2 and stores the calculated result in an operation address storing register 5. A non-operation address storing register 4 occasionally carries the non-operation range address digit part and stores the carried part on the basis of a non-operation address control signal inputted from the external. Consequently, an address signal corresponding to a test pattern for a required W/R test of an object to be tested is outputted from an OR gate 6.

Description

[Detailed Description of the Invention] [Summary] In a testing machine for information processing equipment, when dividing a test object into arbitrary blocks and testing each block, address value setting and setting for each block is performed using an external control signal. , a control method that automatically sets address values within a block and outputs a test address signal based on their logical sum.

[Industrial application field]

The present invention relates to a testing machine for information processing equipment.

In particular, when testing memory cards equipped with a large number of high-density elements, the test block of the device under test is automatically converted to a predetermined size based on the test pattern.
There is a need for a test address control method that can improve test efficiency.

(Prior Art) The most widely used test address control method has been the control storage 2 shown in FIG.
Writing and reading confirmation test (hereinafter referred to as W/R
For example, address control signals for various test patterns for each memory chip shown in FIG. 4 (bl) for the test may be inputted in advance, and the required test patterns may be commanded as shown in FIG. 3. With this address control signal outputted from the control storage 2, an intra-block address calculation circuit 21 that calculates, for example, the writing of one memory chip or the sequential address order in the test block, and a predetermined bit that stores the result. a block address storage register 3', a block address carry circuit 22 for carrying up the address value of each test block based on the W/R test completion signal in the test block, and a predetermined bit for storing the result. The block address storage register 4 consists of a number of block address storage registers 4, and the two sets of address storage registers 3
'', 4'' and FIG. 4 (al) are each connected by a predetermined number of wires.

Then, according to the address control signal from the control storage 2, the intra-block address calculation circuit 21
adds the address values within the block.

After subtraction or shifting, the calculated value is stored in the intra-block address storage register 3'.

Further, one block address carry circuit 22 is configured to receive the W/R in the test block from the control storage 2.
The address value for each test block is set by the test completion signal, and stored in the block address storage register 4', and the intra-block address value and the block address value are separately output to the device under test.

[Problem that the invention seeks to solve]

In the W/R test of memory cards in which the number of address bits per memory chip has increased due to increased density of memory elements, etc., the number of test blocks can be further increased to an arbitrary number as shown in the dashed line in Figure 4 (aJ). It is desired to shorten the test time by subdividing the test blocks and testing the blocks within the test block simultaneously and in parallel.

However, in the conventional method described above, the number of bits stored in the test block address storage register and the number of wires between this register and the device under test are fixed, making it impossible to divide the test blocks, which is a factor that hinders measures to shorten test time. It becomes.

The present invention aims to provide a new test address control method that does not require changing the wiring between the address register and the device under test even if the size of the test block is changed. .

[Failure to solve the problem]

The above problem is caused by the calculation range address register 1 that stores the number of test address digits as shown in FIG. (hereinafter referred to as the calculation address digit), an address calculation circuit 3 that calculates the address value based on the address control signal from the control storage 2, and a calculation address storage register 5 that stores the calculation result of the address calculation circuit 3. , address digits in test block units (hereinafter referred to as non-operation address digits) from the output of the calculation range address register 1.
The non-operational address storage register 4, whose range can be set to any address value by a non-operational address control signal input from the outside, and the outputs of the operational address storage register 5 and the non-operational address storage register 4 are logically summed and tested. This problem is solved by the test address control system of the present invention, which is configured with an OR gate 6 that outputs an address signal.

[Effect]

FIG. 2 is a diagram illustrating test address control according to the present invention.

In the figure, (a) is 1 of the output of calculation range address register 1.
For example, (b) is an example of the output of the arithmetic address storage register 5, (C) is an example of the output of the non-arithmetic address storage register 4, and (d) is an example of the output (test address signal) of the OR gate 6. be.

The example in FIG. 2 shows an example in which the upper 8 bits of the address specify a test block unit, and the lower 24 bits specify an address within the test block unit.

In the present invention, as shown in FIG. 2 (al), an arbitrary calculation range address digit number is first set in the calculation range address register 1.

The part where the bit "1" is set is the operation address digit part, and the part where the bit "0" is set is the non-operation address digit part.

Next, among the test address digits of the DUT output from the calculation range address register 1, for the calculation address digits whose signal is "1", various W/ The address calculation circuit 3 is activated by the address control signal corresponding to the R test pattern.
Addition, '$i calculation, or shift operation is performed to set the address value within the block, and the result is stored in the arithmetic address storage register 5, as shown in FIG. 2(b).

On the other hand, for non-operational address digits for which the output of the operation range address register 1 shown in FIG. 2(al) is 0'', the non-operation address storage register 4 is Carry storage is performed as needed by the non-operational address control signal from .

Then, the arithmetic address part is output from the arithmetic address storage register 5, and the non-arithmetic address part is output from the non-arithmetic address storage register 4, respectively, and the OR gate 6 corresponds to the address configuration of the DUT shown in FIG. 2(d). By obtaining the test address signal, it is possible to arbitrarily change the size of the test block using fixed wiring.

That is, when increasing the test block unit, the non-operational address digit portion shown in FIG. 2(a) is made smaller, and the operational address digit portion is made thicker.

Conversely, when reducing the test block unit, the non-operational address digit portion shown in FIG. 2(a) is made larger and the operational address digit portion is made smaller.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing a test address system according to this embodiment.

In the figure, the calculation range address register 1 stores the test unit of the test block 7 of the test object and the number of test address digits in the test block, as shown in FIG. 4 (f8). The control storage 2, which consists of several RAMs, manually inputs various W/R test patterns in the test block shown in FIG. The address arithmetic circuit 3 outputs the data from the control storage 2 regarding the arithmetic range address digit part where the digit signal is "1" out of the number of test address digits output from the arithmetic range address register 1. The calculated address storage register 5 calculates the address order in the test block based on the address control signal for the required test pattern. The memory and non-operation address storage register 4 stores the non-operation range address digit of which the digit signal is "0" outputted from the operation range address register 1 by an external control signal, for example, a test in the test block. The OR gate 6, which performs carry storage in response to a signal such as completion, performs the logical sum of the output of the operation range address storage register 5 and the output of the non-operation range address storage register 4.

Then, the OR gate 6 and the test object shown in FIG. 4 (al) are connected by a predetermined number of wires.

When an arbitrary calculation range address digit number is input to the calculation range address register 1 as shown in FIG. 2(a), the address calculation circuit 3 is controlled by the address control signal from the control storage 2, ), the calculation range address digit part is calculated into "X" and stored in the calculation address storage register 5.

Further, the non-operational address storage register 4 carries up and stores the non-operational range address digit part as needed, as shown in FIG. 2 (C1), in response to a non-operational address control signal from the outside.

The OR gate 6 outputs an address signal corresponding to a test pattern for the required W/R test of the test object shown in FIG. 2 (dl).

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to test the test object by dividing it into blocks of an optimal arbitrary size with an extremely simple configuration, and as a result, the time required for testing the test object can be significantly shortened. It is expected to have economical effects and is extremely useful in practical terms.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a test address control method according to an embodiment of the present invention, FIG. 2 is a diagram illustrating test address control according to the present invention, and FIG. 3 is a block diagram illustrating a conventional test address control method. FIG. 4 is a diagram illustrating a conventional test object and its test pattern for W/R testing. In the figure, 1 is a calculation range address register, 2 is a control storage, 3 is an address calculation circuit, 3' is an intra-block address storage register, 4 is a non-operation address storage register, 4' is a block address storage register, and 5 is a block address storage register. Arithmetic address storage register; 6 is an OR gate; 7 is a test block; 8 is a memory chip; 21 is an address arithmetic circuit for the block; 22 is an address carry circuit for the block; Also published I information 10,000 formula book o, y7th 1st figure 2 figure city [vermilion test armpit atsushi city 1% method] ゛ low whistle
3 Figure (Q) (b)

Claims (1)

[Claims] An arithmetic range address register (1) for storing the number of test address digits, and an address for calculating an address value based on the value of the arithmetic range address register (1) and the address control signal of the control storage (2). an arithmetic circuit (3);
an arithmetic address storage register (5) that stores the arithmetic result; and a non-arithmetic address storage register (5) that extracts a non-arithmetic address digit from the output of the arithmetic range address register (1) and sets an arbitrary address value using an external control signal.
4) and an OR gate (6) that takes the logical sum of the output of the arithmetic address storage register (5) and the output of the non-arithmetic address storage register (4), and sets the number of digits of an arbitrary arithmetic range address to the arithmetic range. A test address characterized in that by setting in an address register (1), a calculation range address part and a non-calculation address part of a test address signal can be arbitrarily set in accordance with the address configuration of the object under test. control method.