JPS61204746A - Semiconductor device - Google Patents

Abstract

PURPOSE:To execute easily and exactly a timing test by setting temporarily a test data which is bypassed from an input/output point, in a register,and inputting and outputting it to a semiconductor array by reducing the variance of delay time between a tester and the semiconductor array. CONSTITUTION:A data which is read out of the output point 16 of a device 1 is compared with the expected value of a tester, and the result of the test is judged. In this case,the timing for testing a memory array 6 can be determined by a pulse signal which is inputted to each set timing line. Input/output data of the memory array are set to registers 11-14 by the pulse signal, therefore, the variance of the delay time extending from the tester to the registers 11-14 is eliminated. In this way, the timing test can be executed exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device on which timing tests can be easily performed, and in particular to LSI chips or semiconductors suitable for timing tests on memory arrays embedded in logic circuits and other semiconductor arrays. Regarding equipment.

[Background of the invention]

Conventionally, a semiconductor device in which a memory array is embedded in a logic circuit has a memory array as described in Japanese Patent Publication No. 54-15650.
In order to easily test the array, a means for bypassing the logic circuit has been provided to directly input and output test data to the array. However, in this case, although there is an advantage that all signals input and output to the memory array can be directly input and output from the tester to the memory play, no particular consideration is given to variations in the delay time of the signals that occur during this time, and the accuracy It was unsuitable for timing testing of high memory arrays.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can easily perform highly accurate timing tests on semiconductor arrays such as memory arrays embedded in logic circuits.

[Summary of the invention]

The present invention provides a register that holds input/output signals of a semiconductor array, a set timing of the register, and a bypass wiring that connects the register and an input/output point, and once bypassed test data is transferred from the input/output point. By setting it in a register, the delay time variation between the tester and the semiconductor array is reduced and input/output to the semiconductor array is performed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing the overall configuration of a semiconductor device (semiconductor device) 1. As shown in FIG. Device 1 includes a plurality of logic circuits 2.3.4, 5. and a memory array 6. Each of logic circuits 2 to 5 may be any combination of logic circuits. Memory array 6 is 1024 addresses x 9 bits in this embodiment, but for the purpose of the present invention, memory array 6 is 1024 addresses x 9 bits. size is not an issue. Device l also has address registers 11 . WE register 12, write data
Register 13. and the read data register 14 that receives the output signal of the memory array 6 and the cellar 1 of each register.
Timing lines ADST, WEST, WDST, RDST
@- Provided.

The input points of the logic circuits 2 to 4 are generally indicated by the number 15, and the output points to the external circuit are indicated by the number 16.

In addition, bypass wiring that directly connects the input/output points 15 and 16 and the registers 11 to 14, and the address selector 7
, a WE selector 8, a write data selector 9, and a read data selector 10. Each selector 7-1
0 is normal mode, logic circuits 2 to 5 and registers 11 to 14
A test is performed in which the input/output points 15 and 16 are connected to the registers 11 to 14 through the bypass wiring in the test mode.

Next, the operation will be explained. To perform the test, each test line is set in a test mode in advance, and the initial input/output points 15 and 16 are directly connected to each of the registers 11 to 14 via bypass wiring.

First, in order to perform a write operation, the write enable line WE is turned on, and test patterns generated by the tester are inputted to the address lines AO to 9 and the write data lines WO to 8 from the input point 15, respectively. Then, pulse signals are applied to set timing lines ADST, WEST, and WDST, and the input signals are set in registers 11 to 13 and input to memory array 6.

Next, in order to perform a reading operation, the WEB is turned off.

A test pattern generated by the tester is input to address lines AO-9 from input point 15. These input signals provide pulse signals to ADST and WEST in the same way as in the write operation, are set in register 2.3, and access memory array 6. Data read from memory array 6 is taken into register 14 all at once by a pulse signal applied to RDST.

As a result of the above, the data read from the output point 16 of the device I is compared with the expected value of the tester, and the tester result is determined.

The timing for testing the memory array 6 is
It can be determined by the pulse signal input to each set timing line.

Since the input/output data of the memory array is set in the registers 11 to 14 using the above pulse signals, it is possible to eliminate variations in the delay time from the tester to the registers 11 to 14 and perform accurate timing tests. can.

In the above embodiments of the present invention, an example of performing a timing test on a memory array has been described; however, the present invention is not limited to memory arrays and can equally be applied to other semiconductor arrays. Needless to say.

[Effects of the Invention] According to the present invention, it is possible to easily perform an accurate timing test, thereby increasing the reliability of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the semiconductor device of the present invention. 1... Semiconductor device, 2, 3.4.5... Logic circuit, 6... Memory array, 7.8.9
゜10...Address selector, WE selector, write data selector, read data selector. Il, 12.13.14...address register. WE register, write data register, read data register, 15.16... Input point, output point. Figure 1

Claims (1)

[Claims] (1) In a semiconductor device having an input/output point for inputting and outputting from a semiconductor array, a logic circuit, and an external circuit, a first register holds an input signal to be supplied to the semiconductor array, and a first register from the semiconductor array. A second register that holds the output signal of the first register is provided, and the set timing of the first and second registers and the input signal of the first register are directly input from the input/output point. By providing means for bypassing the logic circuit in order to directly output the output signal of the second register to the input/output point, A semiconductor device characterized by performing a timing test.