JP2622720B2 - Fail bit analysis method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail bit analysis method, and more particularly, to a fail bit analysis method for storing fail bit information of a memory device under test (hereinafter, MUT) in a memory test system. The present invention relates to an improvement of a fail bit analysis method that can easily analyze a fail position from data.

[Prior Art] In general, in a memory inspection system, specific data is written to each address of a MUT, and then stored data at each address of the MUT is read and compared with expected value data (write data). Write (mark) "1" data to the corresponding address of the fail bit memory. In this case, the specification of the write address of the fail bit memory is performed using the address signal for specifying the read address of the MUT as it is. Then, by analyzing the storage data (fail bit information) of the obtained fail bit memory, a method of rescuing the fail bit of the MUT, a determination of the resilience or not, and the like are performed.

In this case, the fail bit memory normally has a memory space of the same capacity as the MUT, and only marks a location where a defect has occurred in a one-to-one correspondence and stores an address fail. If the capacity is larger than that of the fail bit memory, the capacity of the fail bit memory will be exceeded. Therefore, there is a case where the fail bit data is compressed and the data is written to the fail bit memory.

[Problem to be Solved] Generally, the memory cell group in the MUT has the number of input / output bits (I / O
), And the number of divisions is 2 n (n = 1, 2, 3,...), So that the address signals (usually in the X direction and Y direction) Some bits of the two-dimensional address signal in the direction are bits for mat selection. On the other hand, the relief of the fail bit of the memory device is generally not performed in units of one bit, but is prepared in advance in the memory device in units of corresponding address bit groups (lines in the X or Y direction) of a plurality of mats. This is done by allocating the rescue redundant line that has been used. That is, a plurality of mats are connected in parallel to treat these reliefs as a common one. Therefore,
For this rescue, it is necessary to analyze the defective address and the defective bit position (bit position as the storage digit position) and perform rescue assignment. However, when all fail bits are taken in as they are, the fail bit rescue is performed. There is a disadvantage that the line analysis processing is troublesome. In particular, when the storage capacity of the memory device is increased recently, such a problem becomes more problematic.

An object of the present invention is to solve such a problem of the prior art, and an object of the present invention is to provide a fail bit analysis system which can efficiently analyze a fail bit.

[Means for Solving the Problems] A feature of the fail bit analysis system of the present invention for achieving such an object is that fail bit data composed of a plurality of bits generated in parallel and obtained from a memory device under test is obtained. Select at least one bit,
It has a mask circuit for masking other bits, a data compression circuit for compressing to a fraction of the plurality of bits of fail bit data, and a parallel input port of a number corresponding to the plurality of bits of fail bit data. A fail bit memory and / or a fail bit data compressed by a data compression circuit and / or a fail bit data masked by a mask circuit are received and selected to a selected one of a plurality of input ports of the fail bit memory. And a data selector for transmitting data selected in accordance with the selection condition of the above. The input port selected by the data selector is provided with fail information or mask information of the fail bit data compressed corresponding to the access address of the memory device under test. Of failed bit data Storing yl information, and performs a fail bit analysis based on a predetermined selection condition and access address therewith stored fail information is selected via the input port.

[Operation] As described above, the fail bit memory having the number of parallel input ports corresponding to the plurality of bits of the fail bit data, and at least one bit selected by the selected input port of the plurality of input ports of the memory By providing a data selector for transmitting the above-mentioned fail bit data, fail information selected by either or both of the compression processing and the mask processing is stored in the position of the input port selected by the data selector of the fail bit memory. be able to.

Thus, fail information under different combination conditions depending on either the compression condition or the mask condition or both can be stored in the input ports of different fail bit memories.

For example, information obtained by compressing the fail information of the entire OR condition into one bit is obtained, and the actual storage position is specified based on the fail information obtained under the other conditions from the address where the fail information is stored. Things can be done easily.
Also, if fail information is fetched once without performing mask processing and compression processing, fail bit information of only the portion corresponding to the input port of the failed bit can be obtained. The failure analysis can be omitted and the failure analysis can be performed in the data range of the input port.

As a result, there is no need to handle the data of all the bit storage areas of the fail memory at once, and the analysis processing is performed by obtaining the data of the conditions required for the analysis as the data at the position corresponding to the specific input port as the analysis target data. be able to.

In particular, since there are not many locations (addresses) where defects occur in the MUT, for example, compressed fail bit information is obtained, thereby obtaining an address of a defect position, and obtaining masked fail bit information. In this case, when the information on the bit position as the digit position of the defect is obtained, both the address of the defect and the information on the bit digit position are obtained. In this data processing, the compressed data of 1 / integer and the mask processing data obtained in accordance with the address are sufficient, so that the overall data analysis processing amount can be reduced.

Further, since the amount of processing of the fail bit information at one time is small, the capacity of the fail bit memory can be reduced. Fail bit analysis can be performed on a memory that can be compressed and has a larger capacity than the capacity of the fail bit memory.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a fail bit memory circuit to which the fail bit analysis method of the present invention is applied, and FIG. 2 is an explanatory diagram of a fail bit analysis process for determining a repair address.

In FIG. 1, reference numeral 1 denotes an AND gate for selecting fail bit data obtained corresponding to a pin of the MUT, and eight 2-input AND circuits 11, 12, 13, 14, 14, 15, 16, 17, and 18 are provided. Each of the AND circuits 11 to 18 receives, on one input, each bit of 8-bit fail bit data, and receives the output of each stage of the mask register 2 on the other input.

The mask register 2 stores 8-bit data corresponding to each of the AND circuits 11 to 18 and masks a bit other than a fail bit corresponding to a pin selected in advance.
The 8-bit data for masking is set in advance in a controller (not shown) having a CPU or the like.

The fail bit data output of the AND gate 1 selected by the mask processing is input to the data compression circuit 3. The data compression circuit 3 includes four 2-input OR circuits 31, 32, 3 in the first stage.
3 and 34, each AND circuit 11 of the AND gate 1
Of the outputs from .about.18 are received corresponding to one OR circuit. As a result, the fail bit data obtained from the MUT is compressed by half here. Similarly, the two-input OR circuits 35 and 36 at the next stage further compress the data to 1/2, and the two-input OR circuit 37 at the final stage further further reduce the data to 1/2. The data is reduced to 1/8 by the data compression circuit 3.

The respective compressed data outputs of the fail bit data compressed to 1/2, 1/4, and 1/8 at these stages are input to the data selector 5, respectively. The data selector 5 includes eight select gates 51, 52, 53, 54, 55, 56, 57, and 58 having four input terminals for selecting one bit from four bits of data.

Select gate 51 of each select gate is AND gate 1
Of the AND circuits 11 to 18 and the output of the OR circuit at each stage of the data compression circuit 3 are input to four input terminals (bits 0 to 3; The first bit position is described as the 0th bit.), And one bit is selected from these four bits of data. The selection gate 52 is the OR of the last stage of the data compression circuit 3.
Except for the output of the circuit 37, the outputs of the respective AND circuits 11 to 18 of the AND gate 1 and the OR circuits 31 to 36 of the data compression circuit 3 are connected to three corresponding input terminals (first bit to third bit) under OR conditions. One bit is selected from the three-bit data received.

Similarly, the selection gates 53 and 54 are provided except for the outputs of the OR circuits 35 to 37 at the final stage and the second stage of the data compression circuit 3, respectively.
The output of each of the AND circuits 11 to 18 of the AND gate 1 and the OR circuits 31 to 34 of each stage of the data compression circuit 3 is received under an OR condition, and one bit is selected from the 2-bit data. The selection gates 55 and 56, 57 and 58 are ORed by the data compression circuit 3, respectively.
Each AND circuit of AND gate 1 except for the outputs of circuits 31 to 37
The output of 11 to 18 is received under the OR condition, and this 1 bit (third bit) is selected.

The fail bit data selected by each of the selection gates 51 to 58 is input to each data input position D0 to D7 of the fail bit 6 which is a memory having a variable port width, and is stored as fail bit information (mark information). .

Each of the select gates 51 to 58 has a select signal 50 (2-bit configuration) for selecting and outputting one of the four data stored in the select gate (1 bit at a specific bit digit position). Supplied from the controller side, this determines the bit digit position to be selected. A0 to An of the fail bit memory 6 are terminals for receiving an address signal, and 7 is an address signal for specifying a read address of the MUT. Dout is a data output terminal, and this data is read and transferred to a memory on the controller side. WE
Is a write terminal, and 8 is a fail bit write signal generated from the controller side.

 Next, the analysis process will be described.

First, all "1" bit data is set in the mask register 2 so as not to be masked.
The select signal 50 is set so that the 0th bit data of 58 is output from each select gate. Then, the write signal 8 and the address signal 7 are added to the fail bit 6, and
Fail bit data consisting of 8 bits is received and is taken into the fail bit memory 8 in a one-to-one correspondence.

FIG. 2A shows the relationship between the fail bit data (mark information) taken in this case and the storage area of each bit. In the drawing, X indicates a marked defect position. Each area divided in the drawing is a mat area that stores each bit corresponding to D0 to D7.

Through the above processing, a fail bit having the same capacity as the MUT is first obtained as in the conventional case.

Next, the information of FIG. 2A is transferred to and stored in the memory on the controller side, and the information of the fail bit memory 6 is cleared to set the selection gate of the data selector 5 to the third bit. 50 is output from the controller side, and the final output of the OR circuit 37 of the data compression circuit 3 is set via the selection gate 51 so as to be stored in the bit position D0 of the fail bit memory 6.

Next, the write signal 8 and the address signal 7 are applied to the fail bit memory 6 in the same manner as described above, and the fail bit data consisting of 8 bits is received and compressed to 1 bit, and the D0 bit position of the fail bit memory 6 is Is stored in a storage area (mat). FIG. 2B shows the relationship between the fetched fail bit data (mark information) and the storage area of D0 and the bit position, and the fail bit information of the D0 bit storage area at this time. Indicates the address position where the fail bit has occurred.

Next, the fail bit data compressed to 1 bit is transferred to and stored in the memory on the controller side. Then, the address of the marked position of the data compressed to 1 bit is obtained.

Next, the mask data in the mask register 2 and the seventh bit by "1", the other as "0", and only the access address and has been the mark is passed through only the D ₇ of the seventh bit, the fail No bit compression (select signal 50
To select the 0th bit of the select gate to output the data from each select gate), the data is taken into the fail bit memory 6, and the data in the storage area where the D7 bit becomes "1" (marked) Get. This is the data at the defective bit digit position as shown in FIG. Thereafter, in the same manner, the data is set at the defective bit digit position shown in FIG. 9C, and the position at which the mask data of the mask register 2 is set to "1" is selected. Collect fail bit information. In this way, the selective setting of the mask data
It is possible to select a storage area of D0 to D7 and detect whether or not there is a mark there, and obtain defective bit digit position information of a mat having a fail bit and address information thereof.

Therefore, it is not necessary to handle the data of all the bit storage areas of the fail bit memory 6 at one time, and it is possible to obtain the fail bit information of only the bit storage area where the mark stands.

When the compressed data or the masked data is received by the fail bit memory 6, the corresponding port width is set.

By the way, in the example shown in FIG. 2A, the storage location of D2 in the fail bit memory 6 has no defect for the sake of explanation, but there is not always only one area without such a mark. . Therefore, the fail bit analysis process performs the fail bit indicating the bit position (address) of the fail bit compressed to 1 bit as described above without processing the fail bit data corresponding to the capacity of the MUT collected first. This can be performed by obtaining only the bit information and the fail bit information at a certain bit position (storage digit position) of the fail bit in the 1-bit area. Moreover, the information amount of the analysis data is 1 / n (where n is the compression ratio) and 1
Only the bit-compressed data is required, and the data processing amount of the analysis processing is reduced.

The fail bit data corresponding to the capacity of the MUT collected in the first stage will be referred to in the course of analysis processing or other defect analysis as necessary. Does not necessarily need to take all the fail bit data. Therefore, the capacity of the fail bit memory can be set to 1 / n.

That is, a fail bit memory having a 1-bit storage area for 1-bit compression storage is provided and connected to the select gate 51 to obtain 1-bit compressed fail bit information. Then, to connect switches the fail bit memory to the select gate 58, corresponding to the "1" is erected position of the mask data, for example, obtain fail bit information storage area of the D ₇ bits. Similarly, the connection of the fail bit memory 6 is switched to the position of the corresponding selection gate in accordance with the position of "1" of the mask data, and the fail bit information in the bit area is selected by the data selector 5 in the bit region. obtained in any of the bits of D ₆ to D ₀ bits.

By doing so, the capacity of the fail bit memory becomes
It will be only 1 / n of the capacity of the MUT. As a result, large capacity
The fail bit analysis processing of the MUT can be performed with a small capacity fail bit memory, and the analysis processing time can be shortened.

In this embodiment, the fail bit mark data compressed to 1 bit is obtained, but this is achieved by selecting the output of the compression stage of the data compression circuit 3 so that the fail data compressed to 2 bits or several bits is obtained. Bit data can be obtained, and analysis may be performed using such compressed data. That is, the analysis process is not limited to the case of compressing to 1 bit. Further, the received fail bit data is not limited to 8 bits, but may be of various bit configurations such as 6 bits or 4 bits. Further, the input port width of the fail bit memory 6 is set to a width corresponding to the received fail bit data (including the compressed fail bit data). Further, when receiving a fail bit larger than 8 bits, for example, 16 bits, the number of AND circuits of the gate circuit 1 is increased correspondingly, and each OR circuit of the data compression circuit 3 is correspondingly increased. What is necessary is just to increase. Similarly, the bit selected by the mask is not limited to one bit.

As described above, the data compression circuit and the data selection circuit in the embodiment can be realized using various logic circuits. For example, a data latch circuit or the like may be used as the data selection circuit.

Further, the mask processing for masking the fail bit is not limited to the one in the embodiment, and various mask circuits or selection circuits can be used.

[Effects of the Invention] As can be understood from the above description, according to the present invention, the fail information selected by either or both of the compression processing and the mask processing is input to the input port selected by the data selector of the fail bit memory. Since there are not many positions where defects occur in the MUT, for example, compressed fail bit information is obtained, thereby obtaining the address of the defect position, and masking the failed bit. Get information,
Thus, by obtaining information on the bit position of the defect, both the address of the defect and the information on the bit position can be obtained.
In this case, since the data processing amount at this time is one-to-one and the fail bit data is fetched, only one-fourth of the compressed integer data and the mask processing data obtained according to the address are required. It is possible to reduce the amount of data analysis required.

Further, since the amount of processing of the fail bit information at one time is small, the capacity of the fail bit memory can be reduced. Fail bit analysis can be performed on a memory that can be compressed and has a larger capacity than the capacity of the fail bit memory.

[Brief description of the drawings]

FIG. 1 is a block diagram of a fail bit memory circuit to which the fail bit analysis method of the present invention is applied, and FIG.
FIG. 9 is an explanatory diagram of a fail bit analysis process for determining the repair address. DESCRIPTION OF SYMBOLS 1 ... AND gate, 2 ... Mask register, 3 ... Data compression circuit, 5 ... Data selector, 6 ... Fail bit memory, 11-18 ... AND circuit, 31-37 ... OR circuit, 5
1 to 58: Select gate.

Claims (1)

(57) [Claims] 1. A mask circuit for selecting at least one bit from a plurality of bits of a plurality of bits generated in parallel and obtained from a memory device under test and masking other bits, and a plurality of bits of the fail bit data. A data compression circuit for compressing data to a fraction of a bit, a fail bit memory having a number of parallel input ports corresponding to the plurality of bits of the fail bit data, and a fail compressed by the data compression circuit Receiving the bit data and / or the fail bit data masked by the mask circuit and transmitting the data selected according to a predetermined selection condition to a selected one of the plurality of input ports of the fail bit memory. And a data selector. The fail information of the compressed fail bit data or the fail information of the masked fail bit data is stored in the selected input port in correspondence with the access address of the memory device under test, and is stored through the input port. A fail bit analysis method for performing a fail bit analysis based on the selected fail information, the predetermined selection condition in which the fail information is selected, and the access address.