JPH0215960B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memories.

With the development of the semiconductor industry, higher integration has become possible, and the capacity of semiconductor memory has increased to 16k bits, 64k bits, and 256k bits. However, in the manufacturing process of such a large-capacity semiconductor memory, the time required for sorting and testing of manufactured products increases, making it difficult to mass-produce. That is, as the memory capacity increases, the degree of integration increases, so it takes time to sort the wafers. Moreover, the time required for testing may effectively result in an incomplete test. This is undesirable because the larger the capacity, the more thorough testing is required.

The present invention has been made in view of the above circumstances, and its purpose is to provide a memory cell group divided into a plurality of blocks, and to simultaneously select each of the blocks during testing and apply the same input data to these blocks. At the same time as writing, a circuit that reads the written data from each block generates an output in the first state when the data read from each block are all "1" and match, and the data is all "0". and a data detection circuit that generates an output in the second state when the data match and generates an output in the third state when the data do not match. It is an object of the present invention to provide a semiconductor memory characterized in that a pass/fail determination is made.

In other words, the present invention provides a semiconductor memory that can significantly reduce test time by dividing memory cells into a plurality of blocks and selectively driving each block independently or simultaneously using an input/output selection circuit. It is about providing.

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the semiconductor memory is divided into four blocks.

In the figure, block data input circuits 5, 6, 7, and 8 are connected to the input terminals of block groups 1, 2, 3, and 4, in which memory cells are divided into four blocks.
These data input circuits 5 to 8 are connected so as to be selectively controlled by an input block selection circuit 9. An input terminal 10 is connected to the input end of each of the data input circuits 5 to 8 so that data signals such as test signals and memory data are supplied thereto. Further, as is well known, each block group 1 to 4 is connected to be supplied with the outputs of an X decoder and a Y decoder, respectively. moreover,
Block data output circuits 11 to 14 are connected to the output terminals of each block group 1 to 4, respectively, and these data output circuits 11 to 14 are connected to be selectively controlled by an output block selection circuit 15.
At the output terminals of each of the data output circuits 11 to 14,
The input terminals of the data output NAND circuit 16 and the data output OR circuit 17 are connected in parallel. At the output terminal of this OR circuit 17 is a field effect transistor (hereinafter simply referred to as FET) 18.
The output terminal of the NAND circuit 16 is connected to the gate of the FET 19, the input terminal of the inverter 20, and the gate of the FET 21, respectively.
The FETs 18 and 19 are connected in series, that is, their sources and drains are directly connected, and this connection is connected to the monitor output terminal 22. Further, the gate of FET 23 is connected to the output terminal of the inverter 20,
This FET 23 and the FET 21 are connected in series, that is, their sources and drains are directly connected, and this connection is connected to the memory output terminal 24.

Next, the operation of the semiconductor memory configured in this manner will be explained. Each block group 1 to 4 has an X in common.
X and Y address selection signals from data and Y data are input. In addition, the input block selection circuit 9
The output block selection circuit 15 simultaneously controls selection, and can select all blocks at the same time or only one block.

First, the test operation of the semiconductor memory will be described. The input block selection circuit 9 and the output block selection circuit 15 select simultaneously. for example,
Test input signal to each block selection circuit 9, 15
Assume that control is performed such that when Ti is set to high level, all blocks are selected at the same time, and when Ti is set to low level, only one block is selected by two address signals. A high level signal is sent from each output of each block selection circuit 9, 15 to each data input circuit 5-4 so as to simultaneously test each block group 1-4.
8 and each data output circuit 11-14. In this state, the test data signal is input to input terminal 1.
0, this data is applied to input circuits 5-
8 to memory blocks 1 to 4, respectively. Next, the data written in each memory block 1-4 is read out via output circuits 11-14 and applied to the input of OR circuit 17, and also applied to the input of NAND circuit 16. The output of the OR circuit 17 is applied to the gate of the FET 18, and the output of the NAND circuit 16 is applied to the gate of the FET 19. As a result, the FETs 18 and 19 are switched and controlled, and the potential of the monitor output terminal 22 is changed. That is, if the outputs of each data output circuit 11 to 14 are all "1", "1" is output to the monitor output terminal 22, and if all the outputs are "0", "0" is output to the monitor output terminal 22. ,
Furthermore, when the output data of the data output circuits 11 to 14 do not match, the outputs of the NAND circuit 16 and the OR circuit 17 both become "1", and at this time, the FET is
If the ratio of 18 and 19 is determined, three values of "1", "0" and an intermediate potential are output to the monitor output terminal 22. Note that when the monitor output terminal 22 reaches an intermediate potential, it means that at least one of the four blocks is defective and three or less of the blocks are defective. Even if "1" or "0" is output to the monitor output terminal 22, it is necessary to compare whether it matches the written expected value. In this embodiment, even if the data read simultaneously from each memory block all match, the monitor output will be different when the data match as "1" and when the data match as "0". The output potentials of the terminals 22 are set to different states of "1" and "0", respectively. Therefore, depending on the output state of the monitor output terminal 22, it is possible to check whether the written expected value and the read data match or do not match. When tested in this way, it takes one-fourth the time to test all the bits of a semiconductor memory. Here, the reason why the two output terminals, monitor output terminal 22 and memory output terminal 24, are provided is that the monitor output terminal 22 is an output terminal for evaluating the results of the above-mentioned test, and each block group 1 to 4
This is to detect defects in one or more blocks and three or less blocks. The other memory output terminal 24 is used as an output signal of the semiconductor memory.

Next, to explain the case of operating as a semiconductor memory, the test input signal Ti to each block selection circuit 9, 15 is set to a low level, each block selection circuit 9, 10 selects one block at a time, and selects one block at a time. By controlling the block to be set to a high level, it operates in the same manner as a conventional semiconductor memory, and the memory output selected from among the memory outputs of the four blocks is obtained from the memory output terminal 24. be.

In the above embodiment, the case where the data is divided into four blocks has been described, but the number of blocks is not limited to four, and the number of blocks may be selected as appropriate depending on the relationship between the memory capacity and the test time. Further, the logic operation circuit and the output circuit may be configured in one system regardless of the number of blocks, or may be divided into a plurality of circuits.

As detailed above, according to the present invention, a memory cell is divided into a plurality of blocks, and each block is selectively driven by an input/output selection circuit either independently or simultaneously, thereby significantly reducing the test time. This makes it possible to shorten the test time to 100%, and has the effect that all bits can be tested even when ultra-large capacity memories are used.

[Brief explanation of drawings]

The figure is a circuit configuration diagram for explaining one embodiment of the present invention. 1 to 4... Each block of memory cells, 5 to 8...
...Block data input circuit, 9...Input block selection circuit, 10...Data input terminal, 11-14
...Block data output circuit, 15...Output block selection circuit, 16...NAND circuit, 17...OR circuit, 18, 19, 21, 23...FET, 2
0...Inverter.

Claims (1)

[Claims] 1 A group of memory cells divided into a plurality of blocks, a circuit that simultaneously selects each of the blocks during testing, writes the same input data to these blocks, and reads the written data from each block; When the read data are all “1” and match, the first state output is generated, and when the data are all “0” and match, the second state output is generated and the data match. 1. A semiconductor memory comprising: a data detection circuit that generates an output in a third state when the data detection circuit is not in use; and the quality of the memory is determined based on the output state of the data detection circuit.