JPS6235199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device that automatically detects bit errors caused by fixed defective bits or incidence of alpha rays, etc., and corrects errors in multiple bits simultaneously. The present invention relates to a semiconductor memory device with a built-in correction circuit.

Conventional technology and problems Conventionally, in a semiconductor memory device, a spare repair bit line is provided, and fixed defective bit lines generated during the manufacturing stage are replaced with repair bit lines to repair fixed defective bit lines and the device can be repaired. There are products designed to improve yield. However, in a semiconductor memory device with such a configuration, defective bits are replaced with repair bits using a dedicated circuit, a laser device, etc., so fixed defective bits that occur during the manufacturing stage can be repaired, but alpha rays and other There is a drawback in that it is impossible to correct non-fixed bit errors caused by incidence.

Purpose of the Invention The present invention has been made to solve these drawbacks, and its purpose is to relieve both fixed defective bits and non-permanent defective bits in a semiconductor memory device that reads multiple bits simultaneously. It's about trying to get it. For this reason, the semiconductor memory device according to the present invention incorporates a circuit for correcting bit errors, and simultaneously performs error correction of the number of stored information corresponding to the number of output information of the semiconductor memory device using as small a circuit as possible. This is how it was done. This will be explained in detail below.

Principle of the Invention FIG. 1 is an explanatory diagram of the principle of bit error correction in the present invention, in which individual information memory cells a ₁ to _{a 36} connected to each word line are divided into two groups, namely a horizontal group and a vertical group. information memory cells that form a horizontal group and a vertical group (for example, a ₁ to a ₆ , a ₁ , a ₇ ，
This figure shows a configuration in which test memory cells b ₁ to b ₆ and c ₁ to c ₆ are provided to store test information for ₍ a ₁₃ , a 19 , a ₂₅ , a _{31 ,} etc.). For the sake of simplicity, here, we will consider a case where the test information is parity information, the test memory cells b ₁ to b ₆ store horizontal parity information, and the test memory cells c ₁ to _{c 6} store vertical parity information. .

According to such a configuration, for example, in order to correct an error in the information stored in the information memory cell _a6 , the horizontal group (bit line group) of the information memory cells _a1 to _a6 , the test memory cell _b1 , and the A memory cell group h consisting of a memory cell group h and information memory cells a ₆ , a ₁₂ ,
A parity check is performed on both the vertical group (bit line group) of a ₁₈ , a ₂₄ , a ₃₀ , and a ₃₆ and the memory cell group i consisting of the test memory cell c ₆ , and a parity error occurs in both. It is sufficient to invert the stored information only when the situation occurs. Error correction is performed within the memory by applying the above error correction principle to information memory cell a and test memory cells b and c, which are simultaneously activated by one word line d, as shown in Figure B. becomes possible. Furthermore, in a storage device that simultaneously reads information stored in a plurality of information memory cells, error correction based on the above-mentioned principle may be performed simultaneously on each information memory cell to be outputted. In FIG. 1, e is a bit line, and f and g are test bit lines.

By the way, in FIG. 1, for one information memory cell that requires error correction, two memory cell groups (one horizontal group and one vertical group) are selected and the parity is corrected. You need to check each one. Therefore, in a multi-bit simultaneous read semiconductor memory device in which there are a plurality of error correction target information memory cells, generally the second
Twice the number of memory cell groups must be selected and the same number of parity checks performed. For example, in order to perform error correction on four information memory cells at the same time, eight memory cell groups are selected,
It is necessary to perform 8 sets of parity checks, and in order to perform error correction on 8 information memory cells at the same time, 16 memory cell groups must be selected and 16 sets of parity checks must be performed. .

FIG. 2 is an explanatory diagram of one method for solving such a problem, and shows a method for selecting four information memory cells that need to be subjected to error correction at the same time. In Fig. 2, a ₁ to _{a 16} are information memory cells, b ₁ to b ₈ and c ₁ to c ₈ are test memory cells, and the information memory cells consisting of 8 x 8 are simultaneously tested for errors. The four information memory cells undergoing correction are designated by the same reference numerals. In this way, each bit line group is configured to include information memory cells of a plurality of bit line groups of the other bit line group, and the information memory cells commonly included are subjected to error correction, that is, information to be read out simultaneously. By using memory cells, it is only necessary to select four sets of memory groups and perform the same four sets of parity checks in order to correct errors in four information memory cells. For example, to perform error correction on four information memory cells with code _a6 , it is sufficient to select four memory cell groups with codes h, i, j, and k, and perform a parity check on the same four groups. The amount of hardware constituting this part can be reduced.

FIG. 3 is a diagram showing a method for selecting eight information memory cells that require simultaneous error correction. The same reference numerals as in FIG. 2 indicate the same parts;
The same reference numerals are given to the eight information memory cells that perform error correction at the same time. With such grouping, for example, to perform error correction on eight information memory cells with code _a6 , it is necessary to select six memory cell groups with codes h to m and select the same six sets of parity check. 2, and it is possible to reduce the amount of hardware constituting that part, as in FIG. 2.

In general, the above-mentioned hardware reduction effect is achieved by ensuring that, in the bit line groups of two bit line groups, at least one bit line group includes information memory cells of multiple bit line groups of the other bit line group, and that the common This can be obtained by making the information memory cell included in the error correction target one of the error correction targets.

Embodiment of the Invention FIG. 4 is a block diagram of a main part of an apparatus according to an embodiment of the present invention, and corresponds to an example in which 4-bit storage information is handled at the same time, and corresponds to the selection method shown in FIG. In the figure, a is an information memory cell, b is a test memory cell (horizontal group), c is a test memory cell (vertical group), d is a word line, e is a bit line,
f is a test bit line (horizontal group), g is a test bit line (vertical group), and S ₁ and S ₂ are two horizontal group memory cell groups (bit line group) from among a plurality of bit lines. This is a selector for selecting a vertical memory cell group (bit line group), and this control is performed according to an externally input address signal. Similarly, _S3 and _S4 are selectors for selecting test memory cells related to the selected bit line group, _P1 to _P4 are parity check circuits,
A ₁ to _{A 4} are AND gates, E ₁ to _{E 16} are exclusive OR gates, and G ₁ , G ₃ , G ₅ , G ₇ , G ₉ to G ₁₂ are gates that turn on at a certain timing during writing. , G ₂ , G ₄ ,
G ₆ and G ₈ are gates that turn on at a certain timing during reading, OUT ₁ to _{OUT 4} are output terminals, IN ₁ to _{IN 4}
is an input terminal.

To explain an example of the correspondence with FIG. 2, parity check circuit P ₁ corresponds to memory cell group h, parity check circuit P ₂ corresponds to memory cell group j,
Parity check circuit _P3 checks the parity of memory cell group i, and parity check circuit _P4 checks the parity of memory cell group k. Therefore, the correction signals of the information memory cells 6 _hi , 6 _hk , 6 _ij , 6 _jh appear at the outputs of the AND gates A ₁ , A ₂ , A ₃ , A ₄ , respectively, and the exclusive OR gates E ₁ , E The outputs of ₂ , E ₃ and E ₄ are the corrected information memory cells 6 _hi , 6 _hk , 6 _i
j , 6 _jh appears. Also, exclusive OR gate
E ₉ , E ₁₀ , E ₁₁ , and E ₁₂ need to rewrite the information of the test memory cells of memory cell groups h, j, i, and k, respectively, using the outputs of exclusive OR gates E ₅ to _{E 8} This is to determine whether or not. This memory operation will be explained below.

first. Clear the stored information in all information memory cells a and test memory cells b and c.

During reading, the information stored in the information memory cells and test memory cells connected to the selected word line appears on bit line e and test bit lines f and g. Among them, 4 are subject to correction.
There are 4 bit line groups (2 horizontal groups, 2 vertical groups) that each bit line information is related to.
set) and four test bit lines are connected to selector S ₁ ~
It is selected in step _S4 , and the stored information is input to parity check circuits _P1 to _P4 , where a parity check is performed. And four parity check circuits P ₁ ~
By sharing part of the output of _P4 , AND gates _A1 to _A4 generate correction signals for respective output information, and exclusive OR gates _E1 to _E4 correct the output information. Also, the corrected output information via gates G ₂ , G ₄ , G ₆ and G ₈ is stored again at the original position.

In addition, during writing, the stored information of the write address before writing is read in the same way as when reading, and that information and the write information applied to input terminals IN ₁ to IN ₄ are combined by exclusive OR gates E ₅ to E ₈ . compare. Then, using this comparison result, gates G ₁ , G ₃ , G ₅ , and G ₇ are enabled at a certain timing during writing.
At the same time, the information stored in the test memory cells related to the four write addresses is updated using exclusive OR gates _E9 to _E16 . For example, 4 information memory cells
In a write in which only the information of a _hi of a ₆ is changed, only E ₅ , E ₉ , and E ₁₁ of exclusive OR gates E ₅ to E ₁₂ become “1”, and the memory cell group h , i _{are changed} .

In the above embodiment, parity information is stored in the test memory cell, so it has only a 1-bit error correction ability, but by storing other test information, it has an error correction ability of 2 or more bits. It is also possible. Further, although an example has been described in which the bit lines are assigned to two groups (horizontal group and vertical group), it is of course possible to assign each of a plurality of bit lines to three or more groups.

Effects of the invention As can be seen from the above explanation, according to the present invention,
Information memory cells are assigned to each of a plurality of groups, and a memory cell for inspection is provided to simultaneously correct errors in information stored in a plurality of information memory cells. It is also possible to repair bit errors (non-fixed bit errors) caused by the incidence of such errors.
Therefore, the present invention can be applied to a semiconductor memory device that outputs other than 1 bit, such as a byte output memory LSI or a memory, in which 4 bits of information are read out in parallel and the output is 1.
If applied to a memory LSI or the like that operates in a nibble mode in which data is serially executed bit by bit, it will be very effective in improving its reliability and yield. Furthermore, if the information memory cell selection method shown in FIG. 2 or 3 is adopted, the amount of hardware can be reduced, and errors in multiple pieces of stored information can be corrected with a small additional circuit. can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of error correction in the present invention, FIGS. 2 and 3 are diagrams showing examples of different methods of selecting information memory cells in the present invention, and FIG. 4 is a main part of the device according to the embodiment of the present invention. It is a block diagram. a is an information memory cell, b is a test memory cell (horizontal group), c is a test memory cell (vertical group), d
is a word line, e is a bit line, f is a test bit line (horizontal line), g is a test bit line (vertical line), h,
j, l, m, i, k are memory cell groups, S ₁ ~
_S4 is a selector, _P1 to _P4 are parity check circuits,
A ₁ to _{A 4} are AND gates, E ₁ to _{E 16} are exclusive OR gates, and G ₁ to _{G 12} are gates that are enabled at a certain timing.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device having an information memory cell for storing information and a plurality of bit lines and word lines, each of the plurality of bit lines belongs to each of a plurality of bit line groups, Inspection bit lines corresponding to the total number of bit line groups when bit lines are grouped in units of a predetermined number in all bit line groups, and bit lines connected to each of the inspection bit lines and activated by the word line. a plurality of test memory cells, means for storing test information regarding a plurality of bit information to be stored in the information memory cells in the test memory cells; A selector for selecting a bit line group and its related bit line for inspection, a parity check means corresponding to each bit line group, Information memory cells connected to each of a plurality of bit lines belonging to each bit line group, one selected from each bit line group, and information memory cells connected to the word line and corresponding to each of the selected bit line groups. means for collectively inputting information on the test memory cells connected to each of the test bit lines to which they belong to the parity check means corresponding to the bit line groups to which they belong; and an output from the selector. 1. A semiconductor memory device comprising: error correction means for collectively correcting errors in information stored in a required number of information memory cells. 2. In the semiconductor memory device according to claim 1, the selector selects a plurality of bit line groups from among the two bit line groups, and selects the selected first bit line group. Error correction is performed using information on a plurality of bit lines that belong to the bit line group of the bit line group and also belong to the bit line group of the selected second bit line group, and the information after error correction is A semiconductor memory device characterized by outputting bit information.