JPS62109299A - Analyzing device for memory inspection data - Google Patents

Abstract

PURPOSE:To reduce an analysis time to specify the position of a fail bit by selecting optional one or more bits of a memory inspection data read out from a fail bit memory, and analyzing the OR data of selected one or more bits inputting them to an analyzing and processing part. CONSTITUTION:Stored data (memory inspection data) at a fail bit memory 10 are read out in order and are inputted to an analyzing device 20. The readout of the memory inspection data is performed by accessing all of the memory devices 11-18 while giving them a common address information 28, and an inspection data of eight bits regarding one word of a memory to be inspected is read out in parallel. A read out data is inputted to an analyzing and processing part 22 through a masking circuit 24 and an OR circuit 26, then being analyzed. The masking circuit 24 is a circuit that makes pass one or more bits from the memory inspection data (eight bits) and masks other bits. The designation for the bit that is made pass is performed with a control information 30 from the analyzing and processing part 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for analyzing memory test data stored in a fail bit memory in a memory test system.

[Prior art] In a memory testing system, the pins of the memory under test are
Only the inspection data at position 111, for example, the bit where the write data and read data do not match (fail focus), is “
1'' data is written into a memory called a fail bit memory. Then, the data stored in the fail bit memory is analyzed by an analysis device.

A conventional example of such a memory test data analysis device is described in the third section.
It is shown and explained in the figure. In this figure, 100 is an 8-bit/word fail bit memory, which is composed of eight 1-pin/word memory elements 101 to 108. 122 is an analysis device that analyzes the data stored in the fail focus memory 100 (memo IJ inspection data).

The data stored in the fail bit memory 100 is sequentially read out and input to the analysis device 122.

This storage data reading is performed for all memory elements rtot~10
8 is accessed by setting common address information +411109 to 5, and 8-bit test result data regarding one word of the memory under test is read out in parallel.

This read data is input to OR circuit 110 and multiplexer 112. The output data of the OR circuit 110 or the output data of the multiplexer 112 is sent to the selection circuit 11.
4 is input. The multiplexer 112 selects one bit designated by the control information 11B of the read data and inputs it to the selection circuit 114. The selection circuit 114 selects the data from the OR circuit 110 or the multiplexer 1.
12 according to control information 118;
The analysis processing section 120 is manually operated.

For example, the memory test data can be analyzed as follows.
: Beware. First, the selection circuit 114 is controlled by the OR circuit 110, and the data stored in each address of the fail pit memory 100 (inspection data for one address of the memory under test) is read out for the nth time. The OR data is sent to the analysis processing unit 120 via the selection circuit 114, and it is checked whether the OR data is "1".

An address whose OR data is "1" means that there is a fail bit on at least one side of 1-, so that address can be stored or the number of addresses including fail pints can be counted. do. However, this is just an example.

Also, if you need to identify the fail bit,
The read data at the address where the OR data is "1" is checked one by one. This process is performed, for example, immediately after the OR data of "1" is detected, or after the middle address check is completed up to the final address.

For example, in the former case, when OR data of "1" is detected, updating of the address is immediately stopped and the selection circuit 114 is switched to the multiplexer 112 side. Then, the control information N11B is used.

1. is sequentially designated, and the read data is sent bit by bit to the data processing section via the multiplexer 112 and the selection circuit 114, and a fail bit is detected.

[Problems to be solved] As described above, in conventional analysis devices, memory test data is either processed as OR data of all bits, or
Either bits were processed sequentially.

Therefore, for example, in order to improve the efficiency of the process for identifying the location of fail bits, after narrowing down the location of fail bits by ORing and analyzing the memory test data by several vias,
It is not possible to adopt a method of checking these few bits one by one.

In addition, the circuit part related to the human power of memory inspection data is
The multiplexer 112 and the selection circuit 114 are included as circuits that need to be controlled, and the control thereof is complicated. Furthermore, the circuit configuration includes three circuits including the OR circuit 110, and cannot be said to be an m1 element.

[Purpose of the Invention] This invention has been made in view of such problems, and its purpose is to improve the circuit portion related to the input of memory test data from the fail bit memory as described above. It is an object of the present invention to provide an analysis device for memo IJQ scan data which is improved so as to shorten the analysis time for specifying the position of a fail bit by a method and which is designed to simplify control and configuration.

[L stage for solving the problem] In order to achieve the first objective, the present invention provides a method for handling the memory test data read from the fail pit memory, α
The circuit part for inputting the memory test data to the analysis processing section is designed so that the analysis processing section manually analyzes the OR data of the selected bits of 1 to I-. It consists of

More specifically, in the memory test data analysis device according to the present invention, the circuit part for human power to the analysis processing section for the memory test data read out from the fail focus memory is separated from the analysis processing section. .

A mask circuit that selectively passes bits of 1 or more 1 of the memory test data specified by α according to the control information obtained, and the data that has passed through this mask circuit are logically ORed and sent to the analysis processing section manually. The present invention is characterized by comprising an OR circuit.

[An arbitrary one or more bits of the memory test data can be selected by the effect mask circuit, and the OR data can be inputted to the analysis processing section.

Therefore, for example, for an address where an error was detected in the OR data of all bits, after ORing several bits to narrow down the position of fail bits,
By checking each bit bit by bit, the analysis time for identifying fail bits can be shortened and the analysis processing of memory test data can be made more efficient.

Of course, by sequentially selecting l bits at a time using the mask circuit, the memory test data can be analyzed bit by bit as in the conventional method.

Furthermore, regarding the circuit portion related to the input of memory test data to the analysis processing section, the constituent circuits are ORed with the mask circuit.
Since it is only a circuit, the configuration is simpler than before, and
The only circuit that needs to be controlled is the mask circuit, and its control is also more central than before.

[See example code and drawings! l(IL, Examples of this invention will be described.

FIG. 1 is a schematic block diagram showing the configuration of an embodiment of a memory test data analysis device according to the present invention. In this figure, 10 is an 8-bit, bit/word fail bit memory into which memory test data is written in the memory testing system, and eight 1-bit/word memories J
It is composed of J'll~18.

Reference numeral 20 denotes an analysis device that analyzes the data stored in the fail bit memory 10 (memory test data). This analysis device 20 is composed of an analysis processing section 22, a mask circuit 24 and an OR circuit 26 related to human input to the analysis processing section 22 for memory test data.

The data stored in the fail bit memory 10 (memory test data) is sequentially read out and input to the analysis device 20. This memory test data is read from all memory elements 11.
.about.18 are accessed using common address information 28 (1-), and 8-bit test data regarding one word of the memory under test is read out in parallel. This read data is input to the analysis processing section 22 via the mask circuit 24 and the OR circuit 26, and is analyzed.

The mask circuit 24 is a circuit that passes one or more bits from the data (8 bits) to the manually operated memory detection and masks other points. The passing bit is specified by the control information 30 from the analysis processing unit 22.

FIG. 2 shows an example of the mask circuit 24. The mask circuit 24 shown here, each bit of memory inspection data /) DO, I) /
, . . . , 1) An anime game in which each of the 7s is human-powered.
) 32o, 327. ..., 327, and control information 3
It is comprised of an rn out of 8J type decoder circuit 34 that decodes 0 and controls AND gates 320 to 327.

The decoder circuit 34 has eight outputs Oo-07 corresponding to each AND gate 320-327, and is coupled to the output of the corresponding AND gate 320-327, respectively. Then, the decoder circuit 34 operates an AND gate (32 o
~327) is set to “1” only on the output (Oo~07) connected to
" level signal is sent out, and the other outputs are held at the "0" level. As a result, only one bit or more of the memory test data specified by the control information 30 is transmitted to the OR circuit 26, and other outputs are held at the "0" level. Bits are masked.

As explained below, the input circuit portion of the memory test data to the analysis processing section 22 has the above-mentioned configuration.
OR data of 1 or 2 or more bits of α of the memory test data can be input to the analysis processing unit 22 and analyzed.

Therefore, in this embodiment, for example, the above-mentioned analysis operation is possible. It should be noted that the above operation is merely an example, and it is natural that the operation is not limited thereto. Furthermore, although the memory test data is such that only the fail bit is "1", this is just one example.

First, control information 30 for passing all bits of memory test data is provided from the analysis processing section 22 to the mask circuit 24. In this state, the analysis processing unit 22 accesses the fail bit memory IO while sequentially updating the address information 28, and sequentially reads out the memory test data.

All bit OR data of the read memory test data is manually input to the analysis processing section 22, and checked to see if it is "1". When the "l" data is detected, the analysis processing unit 22 stores the address information at that time, stops updating the address information +%128, and starts processing for identifying the location of the fail pit.

First, the control information 30 for passing the four bits of the highest order is provided to the mask circuit 24, and the OR data of the four highest bits of the memory test data is inputted to the analysis processing section 22.

For example, if the OR data is "0", this means that no fail pit is included in the 4 bits at the "-" position, and one or more fail pits are present in the 4 bits at the "-" position.

Therefore, the mask circuit 24 is controlled by the control terminal +%130 so as to pass the 1st-order 4 bits one pin at a time, and each bit is checked.

In this way, the '1' bit is detected as a 7-ail bit, and the bit position is stored.

In this case, the number of checks required to identify the location of the fail pit is only five, and the number of checks is considerably reduced compared to the case where all 8 bits are checked one by one.

As described above, according to the present invention, analysis for specifying the location of fail pits can be performed more efficiently in a shorter time than in the past. If the number of vias in the memory test data is larger, the effect of reducing the processing time will be even more obvious.

Keita, analysis processing unit 22! The circuit portion for manually inputting this memory test data is a mask circuit 24 and an OR circuit 26.
It is composed of a circuit, and the circuit configuration is simpler than the conventional one. Furthermore, since the mask circuit 24 is the only circuit that needs to be controlled, control is simpler and simpler than in the past.

Although the embodiments have been described above, the present invention is not limited thereto, and can be implemented by appropriately modifying the internal structure of the mask circuit.

[Effects of the Invention] As is clear from the above description, the present invention includes selecting one or more bits of memory test data read from a fail pit memory using a mask circuit;
This circuit constitutes a circuit section for manually inputting the memory test data to the analysis processing section so that the OR data of the selected l to 1 bits is manually analyzed by the analysis processing section via the OR circuit. For example, regarding an address where an error was detected in the OR data of all bits, OR data of several bits
After narrowing down the location of fail pits by taking the following information, the analysis time for identifying fail pits can be shortened and the analysis processing of memory inspection data can be made more efficient. In addition, the circuitry related to human power for the memory test data analysis processing section consists of only a mask circuit and an OR circuit, making the configuration simpler than before and reducing the need for control. The mask circuit is the only circuit that can be used, and its control can be simplified compared to conventional methods.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of the present invention. 2 is a block diagram showing an example of a mask circuit, and FIG. 3 is a schematic block diagram of a conventional memory detection data analysis device. DESCRIPTION OF SYMBOLS 10... Fail pit memory, 20... Analysis device, 22... Analysis processing device, 24... Mask circuit, 3
0... Control information, 320-327... AND gate, 34... Decoder circuit. Holder S1 applicant

Claims (2)

[Claims] (1) A device for reading and analyzing memory test data from a fail bit memory, in which a circuit part for inputting the memory test data read from the fail bit memory to an analysis processing section is provided by the analysis processing section. 1 of the memory inspection data arbitrarily specified by the control information provided.
An apparatus for analyzing memory test data, comprising a mask circuit that selectively passes the above bits, and an OR circuit that ORs the data passed through the mask circuit and inputs the result to the analysis processing section. (2) The mask circuit has a plurality of gates into which corresponding bits of memory test data are input, and a plurality of outputs for controlling each gate, and one or more outputs specified by the control information according to the control information. 2. The memory test data analysis device according to claim 1, further comprising a circuit that sends a signal for selectively opening the gate to one or more outputs corresponding to the gate.