JPS58189750A - Memory device - Google Patents

Abstract

PURPOSE:To perform the input and output with high efficiency, by using directly the writing and reading programs of a floppy disk to write and read a data. CONSTITUTION:An ROM21 and an RAM20 are divided into plural sectors respectively. When an operation is started, the prescribed track No. and sector No. are supplied through a data bus line 2 and then stored in registers 12 and 13. Furthermore an input/output discriminating signal of data is supplied to a driving/refreshing circuit 15 from a decoder 14 to drive a counter 16. The data on the designated address is written and read out by the numerical values of registers 12 and 13 as well as the counter 16. Therefore, it is possible to write and read the data by using directly the writing and reading programs of a floppy disk 9.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large capacity memory device connected to a so-called microcomputer.

The so-called Microcomputer is configured as follows. In Figure 1, (1) Fi central processing unit & (
CPU), from the CPU (1) to the data/file line (2), control path line (3),
An address path line (4) is derived. Each of these lines (2) to (4) is a read-only memory (ROM) in which the CPU (1) operates.
) (5) and a random access memory (RAM) (6) for data storage. Furthermore, each of these lines (2) to (4) is connected to an input/output circuit (7). Note that αQ is an oscillator that creates the timing of the operation of the CPU (1).

In this device, data from the outside is input to/output circuit (7
) is read into the CPU (1), and then RAM
(6) is added to 4. And ROM (5)! Data is processed according to the program, and the resulting data is taken out to the outside through an input/output circuit (7).

However, in such devices, the storage capacity of the RAM (6) is extremely limited, so it is not possible to handle large amounts of data, such as compilers, editing, etc.
Processing such as sorting cannot be performed.

Therefore, a large-capacity memory device is provided externally, and a predetermined amount of data is input/output to substantially increase the storage capacity of the RAM (6).

An example of such a memory device is a book called a floppy disk.

As shown in Figure 2, a floppy disk is a magnetic disk with a diameter of 8 inches, for example, and has 77 concentric trunks (
0 to 76), with each trunk having 26 sectors (
1 to 26), and each sector can store 128 bytes of data.

And each line (2) from the input/output circuit (7) in Figure 1
~(4) signals are sent to the floppy disk controller (
The FDC (8) drives a floppy disk (9) to input and output data.

That is, the floppy disk (9) from the CPU (1)
) is used or not is supplied to yDc (s) through the address path line (4). In addition, signals specifying the trunk and sector numbers of the floppy disk (9) are sent to the FDC (8) through the r-tapas line (2).
K is supplied. Furthermore, a write or read control signal is passed through the control path line (5) to the FDC (
8). Then, the floppy disk (9) is rotated, the position of the magnetic head 1 is moved, and sector 0 convolution and reading of the designated number is performed through the data path line (2). Note that an identification signal indicating whether the signal on the data/9th line (2) is a trunk number, a sector number, or input/output data is supplied to the FDC (8) through the address path line (4). be done.

In this way, the data on the floppy disk (9) is input and output.

However, in the case of such a floppy disk (9), the time required to reach a designated sector, the so-called access time, is nine times longer than that of a mechanical drive, and input/output cannot be performed efficiently.

By the way, the price of memory elements such as random access memory has decreased significantly compared to when they were first developed, and providing a large number of memory elements is no longer a cost problem.

Therefore, for example, it was considered to increase the capacity of RAM (6) itself, but such a large capacity is not necessary for normal use, and increasing the capacity of RAM (6) would be It was necessary to change the design of the software or hardware of the settings, and there were many problems when using general-purpose CPUs (1) that were already in practical use.

In view of these points, the present invention provides a memory device that can be handled in the same way as a floppy disk and has a short access time.

That is, the present invention has a read-only memory and a random access memory, divides the read-only memory and random access memory into a plurality of sectors, and synthesizes the sector number supplied through the data bus and the output of the built-in counter. This is used as the read-only memory and random access memory address, and reading and writing are performed in units of sectors.

An embodiment of the present invention will now be described with reference to the drawings.

In FIG. 3, it is a gIJFi dynamic type random access memory. This memory (E) has a storage capacity of about 19 yen, which is equivalent to the storage capacity of the data area of one floppy disk.
It has a storage capacity of 0 K-bytes, which is formed, for example, by providing three 64-byte memory sections in parallel.

υ is a read-only memory, and this memory e corresponds to the area in which the !rodram necessary to operate a computer such as a floppy disk operation system is written, and this is, for example, a 64 Kbyte mask. It is formed in ROM.

Furthermore, the address pass line (4) and the empty OROM (5
).

A signal indicating whether RAM (6) or an external memory device is being used is supplied to an address decoder (to) to form a signal corresponding to the respective memory device being used. These signals are stored in the ROM (
5) is supplied to RAM (6) and an external memory device to be described later. The illustrated example shows a case where two external memory devices are provided, one of which is a floppy disk (9) and the other a memory device according to the present invention.

and data path line (2) from input/output circuit (7)
is data area circuit αυ, trunk number Renostar (to)
, connected to the sector number register (6). Furthermore, the data bus line (2) is connected to the address path line (4).
) is supplied to the decoder α rod for identifying whether the signal is a trunk number, a sector number, or input/output data. A signal from the decoder (to) is supplied to the control terminal of this decoder α♦. Then, the decoded signal is transferred to the above-mentioned buffer circuit α theory, register (
6), supplied to the IO drive terminal. Further, a write or read control signal from the control path line (3) is supplied to the amplifier circuit α, the register (6), and the control @ terminal of CL1.

Furthermore, a write or read control signal is supplied to the memory drive and refresh circuit. Further, a signal when the signal on the data bus line (2) from the decoder α♦ is input/output data is supplied to the drive and refresh circuit (to). Further, a signal of, for example, the upper two bits of the numerical value indicating the trunk number from the register (2) is supplied to the drive and refresh circuit (b). Furthermore, a clock signal from an oscillator (7) is supplied to the drive and refresh circuit (to). Then, a signal is sent to this drive and refresh circuit) to control the refresh of the memory IJm and to control the refresh of the memory IJm. At the same time, the output signal of the drive and refresh circuit (g) is supplied to the 128-decimal counter (to).

'Also, the write or read control signal is
Gf) is supplied to the drive circuit α power, and is further supplied to the register (6
) is supplied to the drive circuit αη. Then, a signal from the drive circuit 0f) is supplied to the output terminal of the memory vtυ.

Furthermore, the count value of the counter (2), the value of the track number register (2) mentioned above, and the sector number
are supplied to the synthesis circuit (to). Also, signals from the drive and refresh circuit (to) are supplied to the control terminal of the combining circuit Ql.

The numerical value formed by this synthesis circuit (to) is supplied to the address terminal of the memory (e). Also counter (b) and reno star negative 2. The numeric value is supplied to the address terminal of the memory (C) and the data terminal of the circuit A circuit memory (E) is connected to the data terminal of the circuit A.

And in Memory Kan, (2), Chin! By supplying a signal to the select terminal, one of the three memory sections of the memory QOO or memory (2) is selected, and by specifying an address to the address terminal, writing and reading of the specified address are performed.

First, to explain the normal operation of this circuit, to write a random access message,
The track number and sector number to which writing is to be performed first are supplied through the data/4 line (2). At this time, the track number and sector number identification signals are sent from the decoder α◆ to registers (6) and (
), and the trunk number and sector number are stored in these registers (6) and o3. Furthermore, the upper two bits of the register (6) are set to the drive and refresh circuit (g) and the drive circuit alpha power, and in this case, the signal from the drive and refresh circuit (2) is used to input the memory (
One of the three memory sections 1) is selected.

The data to be written next is supplied through the data bus line (2). At this time, an identification signal for data input/output from the decoder α◆ is supplied to the . The associated signal drives the counter Q. Then, the count value of the counter α → and the track number and sector number stored in the register Q, η are combined into a synthesis circuit (
2) to form the address number of the memo IJH.

Here, the address number is formed by using, for example, the trunk number excluding the upper two bits as the upper pin of the address number, the sector number as the middle bit, and the count value of the counter as the lower bit.

Then, the address trap data designated by the formed address number is stored, and thereafter data for 128/mother byte is stored in 128 consecutive addresses in sequence.

To read out the random access memory (e), the track number and sector number on which alignment is to be performed are first supplied through the r-tapas line (2), and these numbers are stored in the register (6). .

(to), and one of the memory sections in memory (to) is selected. When the data input/output identification signal is supplied from the decoder a♦ to the drive and refresh circuit (b), the counter Qd is driven and the register (a) is activated.

Data at 128 addresses specified by the value of αJ and the count value of counter αQ is sequentially read out.

This read data is supplied to the data path line (2) through the amplifier circuit (1m).

Furthermore, at the start of operation in this circuit, a predetermined track number and sector number are first supplied through the data path line (2), and these numbers are stored in the registers (A) and (Ll. Register α
The signal of the upper two bits of the force is determined by the drive circuit αη,
This value is used to select read-only memory (c).

Furthermore, data input/output signals from the decoder α◆ are not supplied to the drive and refresh circuit (b), and the counter (
(To) is driven, and the register (B) is driven.

The data at the 128 addresses specified by the value in (b) and the count value of the counter (g) is read out in sequence.In this way, the data is stored and read out, and the program is read out. According to the present invention, by supplying the trunk number and the sector number through the data path line (2), 128 addresses not included in this sector can be written or read, and these addresses can be written or read from the above-mentioned floppy disk. It is similar to writing and reading disks.

Further, a program corresponding to the operation system of a floppy disk can be stored in the read-only memory e1, so that it can be treated exactly the same as a floppy disk.

Therefore, the writing and reading programs for the floppy disk (9) built into the CPU (1) and the ROM (5) can be used as they are to write and read data. And in this case, memory (
Since the device (e) is composed of memory elements, there is no mechanical access delay, and input/output can be performed extremely efficiently.

That is, according to the present invention, it is possible to provide a high-speed, large-capacity memory in a microcomputer that has a relatively small built-in RAM and a program for driving a floppy disk without making any internal design changes. can.

Therefore, processing such as layout, editing, and sorting can be performed extremely quickly.

Note that when the scale of the program such as the above-mentioned system is small, the capacity of the read-only memory (2) may be reduced, and the capacity of the random access memory (e) may be increased accordingly.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining a conventional device, and FIG. 3 is a configuration diagram of an example of the present invention. (1) ij CPU
, (2) is the data path line, (3) Fi control path line, (4) h address bus line, (5) H
ROM, (6) FiRAM, (7) #'i input/output circuit, (lIa7'-1/9777 circuit, ←kke trunk number register, a3Fi Ryuta number register, α4
is a decoder, (b) is a drive and refresh circuit, αQ
is a counter, α force is a drive circuit, (To) is a synthesis circuit, and (E) is a random access memory? (trans) is read-only memory.

Claims (1)

[Claims] It has a read-only memory and a random access memory, each of the read-only memory and the random access memory is divided into a plurality of sectors, and the number of the sector supplied through the data bus and the output of the built-in counter are combined and distributed. - A memory device in which reading and writing are performed in units of sectors, with addresses of a read-only memory and a random access memory.