JPS6246493A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a time required for rewriting to a ROM while keeping a complete float by simultaneously carrying out a saving operation of the non- writing data and writing operation of the data in parallel. CONSTITUTION:During rewriting a ROM 2, a selecting signal X0 applied to a data selecting circuit 23 is also applied to latches A, B. Thereby, respective modes of reading and writing of the latches A, B are individually controlled, and during rewriting the memory data, the non-rewriting data D1b erased once is read and is latch B performs a holding and saving operation and the latch A in which the writing data is held performs a data writing externally, simultaneously and in parallel.

Description

[Detailed Description of the Invention] [Technical Field] Jin's invention is applicable to semiconductor integrated circuit device technology and EBP-
ROM (Electrically Erasable and Programmable Memory: EA
- Also called ROM. ) and a digital circuit using an EEP-ROM are formed together.This technology is particularly effective when applied to a semiconductor integrated circuit device in which a digital circuit using an EEP-ROM is formed. This article relates to a technique that is effective when used in combinations.

[Background technology]

For example, a so-called single-chip microcomputer is typical of a semiconductor integrated circuit device in which a memory and a digital circuit are formed together.

These single-chip microcomputers are often used, for example, to be embedded in equipment, and in the past, many of them had built-in ROMs that could not be rewritten, but recently, for example, they have been used for example.Published by Nikkei McGraw-Hill Publishing Nikkei Electronics March 30, 1981 As described in page 80 of the issue (Technical Bulletin), ROMs with built-in nonvolatile memories that can be rewritten in real time have become available. Incorporating such a rewritable non-volatile memory allows the user to freely write the microcomputer's system programs and fixed storage data, depending on the type of controlled equipment, for example. be able to. Now, it has become possible to adapt the same model of microcomputer to a wide variety of uses, making it possible to utilize the mass production effects of semiconductor integrated circuit devices and apply them to a wide variety of small-volume devices. Become.

FIG. 4 shows an example of a microcomputer equipped with an EEP-ROM.

The microcomputer shown in the figure is configured as a single-chip microcomputer, and includes a CPU (central processing unit) 1 as a digital circuit.
and EE as electrically erasable and writable memory.
It has P-ROM2.

The CPUI and EEP-ROM2 are connected to an address bus L1, a data bus L2 . and are connected via a control path L3.

CPU1 receives address Ax and read/write control signal R.
, /W etc. to access EEP-OM2,
data/(, data D via CL 2
1 will be given and received.

The EEP-ROM 2 includes a memory cell array 21, an address decoder 22, latch circuits A and B, a data selection circuit 23, and the like.

The memory cell array 21 has, for example, five memory rows each having two bytes (2.times.8 bits) as one word, and has a total storage capacity of 10 bytes (2 bytes.times.57-words=10 bytes). Dla.

Dlb-Dsa and Dsb each indicate 1 byte of stored data. Each storage data Dla, Dlb to D5a,
D5b is erased and written in units of 2 bytes (1 word).

Latch circuits A and B each hold one byte of data, and as a whole hold one word of data.

In the latch circuits A and B, the storage data of the portion designated by the upper digit of the address AX is temporarily held and saved in units of one word.

The address decoder 22 outputs word selection signals X1 to X5 for selecting any one word of data in the memory cell array 21 based on the upper digits of the address AX.

Along with this, based on the lower digits of the address AX,
A latch selection signal XO for selecting one of the latch circuits A and B is output.

The data selection circuit 23 is a type of switching circuit, and is controlled by the latch selection signal XoK.

FIG. 5 shows an example of operation when replacing the microcomputer 14 with the one described above.

Figure 6 (a), (b), and (C) are EEP-ROM2
When rewriting part of the memory data of
Changes in the state within the EP-ROMZ are shown in stages.

In FIGS. 5 and 6, for example, when rewriting 1' byte of storage data Dal in EEP-□ ROMZ, first, as a first step, address xAxt-EEP-ROM2 is given from the CPUI.

As a result, as shown in FIG. 6(a), the EEP-RO
Target storage data Da from the storage cell array 21 in the MZ
One word data (Dat, Dab) containing 1 is read out and held/saved in latch circuits A and B.

Next, as a second step, the read/write control signal R/W is set to write designation mode at this point. This is k, 6th
As shown in Figure (b), among the latch circuits A and B,
The data held in the latch circuit A selected by the data selection circuit 23])al is rewritten to arbitrary write data Dx.

After this 1. As a third step, as shown in FIG. 6(C)K, the data l)
b is written to the original storage location in storage cell array 21.

In the manner described above, any one byte of data in the EEP-ROM 2 can be specified and rewritten.

However, in the microcomputer mentioned above,
The inventor of the present invention has found that there are the following problems when rewriting the data stored in the EEP-ROM 2.

That is, in the microcomputer mentioned above, EE
When rewriting the stored data in P-ROMZ,
(1) Read the stored data and hold it in latch circuits A and B.
(2) Latch circuit A.

(3) write the data held in the latch circuit to the original storage location; perform the above three operations (1) (21 (3) in stages in a time-sharing manner). Therefore, in order to complete the rewriting of the stored data in the EEP-ROM 2, as shown in FIG. The total time (tl+t2) was required.Then, this total time (tl+t2) was
The appearance of EP-R, 0M2 was the above access time tac. In this way, rewriting the data stored in the EEP-ROM 2 requires much longer time than just reading the stored data. In addition, since the write operation was performed after the stored data had been once read into the latch circuits A and B, if an attempt was made to shorten the above-mentioned rewrite time tac, the time that could be allocated to the write operation would be reduced. , a problem arises in that it becomes difficult to secure sufficient write margin time (write margin).

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device with a built-in EEP-ROM, and to shorten the time required to rewrite the EEP-ROM while ensuring sufficient writing margin time. The goal is to provide technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

That is, when rewriting the stored data in the EEP-ROM, (1) the stored data is read out and held/saved in the latch circuits A and B, and (2) the latch circuit A.

Of the above three operations (1), (2), and (3), (1) and (2) partially rewrite the data held in BK, and (3) write the data held in the latch circuit to the original storage location.
) operations are performed simultaneously in parallel to achieve the purpose of shortening the access time to the EEP-ROM while ensuring sufficient write margin time. .

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a microcomputer to which the present invention is applied.

The microcomputer shown in the figure is basically the same as the one described above. In other words, the micro-
The computer is configured as a single-chip microcomputer and has a CPU (central processing unit) 1 as a digital circuit and an EEP-ROM 2 as an electrically erasable and writable memory. CPUI and E
EP-ROM2 has an address bus L1 and a data bus L2.
, and are connected via a control bus L3.

CPUI, address Ax and read/write control signal R
, /W, etc. to access the EEP-ROM 2t-, and exchange data Dx via the data bus L2.

The EEP-ROM 2 includes a memory cell array 21, an address decoder 22, latch circuits A and B, a data selection circuit 23, and the like.

In the memory cell A1/I21, for example, five memory rows each having two bytes (2 x 8 bits) as one word are arranged, and the memory cell has a total storage capacity of 10 bytes (2 bytes x 5 words = 10 bytes). . Dta.

D1b~])5a and D5b each indicate 1 byte of stored data. Each stored data D1a, 1) 1b to D
5a and D5b are configured to be erased and written in units of 2 bytes (1 word).

Latch circuits A and B each hold one byte of data, and as a whole hold one word of data.

In the latch circuits A and B, the storage data of the portion designated by the upper digit of the address AX is temporarily held and saved in units of one word.

The address decoder 22 outputs word selection signals X1 to X5 for selecting any one word of data in the memory cell array 21 based on the upper digits of the address Ax.

Along with this, based on the lower digits of the address AX,
Above 2. A latch selection signal XO for selecting one of child circuits A and B is output.

The data selection circuit 23 is a type of switching circuit, and is controlled by the latch selection signal Xo.

In addition to the above-described configuration, this embodiment also includes the above-mentioned EEP-
When rewriting ROM2, the above two
□.

The latch circuits A and B of □ are in the lower digits of address AX.
:Thus, only the selected latch circuit is configured to have external data written thereto, and the other unselected latch circuits are configured to have stored data written in the non-rewritten portion of the memory cell 21. Therefore, during rewriting, the selection signal XO applied to the data selection circuit 23 is also applied to the latch circuits A and H. Therefore, latch circuit A.

The read/write mode of B is individually controlled, and when rewriting the stored data, the emergency exchange data Dlb, which is temporarily erased with the rewriting, is read out and the 2-touch circuit BK is held/saved, and the write operation is performed. The operation of externally writing data into the latch circuit where data is held is
It is now possible to perform multiple tasks at the same time.

Figure 2 shows the nine microcomputers mentioned above.
An example of the operation when rewriting part of the data stored in the EEP-ROM 2 will be shown.

In addition, FIGS. 3(a) and 3(b) show that when a part of the data stored in the EEP-ROM 20 is rewritten, the EEP-ROM 20 is
Changes in the state within ROM2 are shown in two stages.

In FIGS. 2 and 3, for example, EEP-ROM2
When rewriting 1 byte of memory data 1) al, first, as a first step, write the address AX from the CPU
and write data DX to the EEP-OM2. At the same time, the read/write control signal R/W is set to write designation mode. Then, as shown in FIG. 3(a)K, the non-rewritten data []) lb which is once erased upon rewriting is read and the latch circuit B4C is held and saved, and the latch circuit AK is written from outside. data])x
The operation of writing is performed at the same time. tb, thisζ
Now, let's move on to the first point mentioned above. Second two-stage operation (1) (
2) are performed simultaneously in parallel.

Therefore, after this first stage, it is possible to immediately enter an operation corresponding to the third stage operation (3)K described above. In the second stage, as shown in the TSA diagram (b), each held data Dx of the latch circuits A and B is
DIb is written to the original storage location in storage cell array 21.

As described above, by performing the write operation from the beginning of the rewrite operation, 9. Any 1-byte data in the EEP-ROM 2 is completed in a short access time (tac=t2). This makes it possible to shorten the time required for rewriting the EEP-ROM 2 (tac) while ensuring sufficient write margin time.

〔effect〕

(1) When rewriting the stored data in the EEP-ROM, (1) Read the stored data and hold/saved the latch circuits A and BK, (2) Partially rewrite the data held in the latch circuits A and H. , (3) Write the data held in the latch circuit to the original storage location. The above three operations (1)
) Out of (2) and (3), the configuration allows operations (1) and (2) to be performed simultaneously in parallel, thereby shortening the access time to the EBP-ROM while ensuring sufficient write margin time. This has the effect of making it possible to convert

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the EEP-
The storage data configuration of the ROM 2 may be a combination other than 2 bytes and 1 word.

[Application field]

Although the invention made by the present inventor is applied to single-chip microcomputers, which is the background field of application, it is not limited to this, and for example, it can be applied to arithmetic processors, communication interfaces, etc. It can also be applied to semiconductor integrated circuit devices for peripheral functions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a single-chip microcomputer with a built-in EEP-ROM to which the present invention is applied, and FIG. 2 is a block diagram showing an EEP-ROM in a single-chip MR computer to which the present invention is applied. FIGS. 3(a) and 3(b) are timing charts showing an example of the rewriting operation of the EEP-ROM. The figure shown in FIG. 4 is a diagram showing an example of the configuration of a computer in a conventional single-chip type bicycle with a built-in BEP-ROM. Figure 5 is a timing chart showing an example of EEPROM rewriting operation in a conventional single-chip microcomputer; Figures 6 (alb) and (C) are diagrams of a conventional single-chip microcomputer. FIG. 4 is a diagram illustrating, step by step, the state when the EEP-ROM is rewritten. 1...CPU (central processing unit), 2...EEP
-ROM, 21...Storage cell array, 22...Address decoder, 23...Data selection circuit, A, B...
・Latch circuit, Ll...Address bus, L2...Data no(nu), L3...Limit bus, Dx...Write data, Ax...Address. one

Claims (1)

[Claims] 1. An electrically erasable and writable nonvolatile memory having a plurality of latch circuits for saving stored data in a data rewriting portion, and rewriting or reading stored data via the latch circuits. A semiconductor integrated circuit device is formed together with a digital circuit that performs the following: when rewriting the stored data, reading non-rewritten data that is temporarily erased due to the rewriting and saving it in a latch circuit;
A semiconductor integrated circuit device characterized in that an operation of externally writing data into a latch circuit that holds write data is simultaneously performed in parallel with each other. 2. When rewriting the non-volatile memory, only the latch circuit selected by the address is written with external data, and the other unselected latch circuits are used to store the non-rewritten portion of the memory. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured to allow data to be written.