JP2000112755A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use an evalution chip in common for plural purposes. SOLUTION: Since the whole or a part of an instruction decoder 8 is composed of a flash memory 8b, an instruction code is easily changed only by rewriting the contents of the memory 8b even in the case of requiring the change and addition of a peripheral circuit with the change and addition of the specification of a microcomputer in the case of executing program evaluation by the evaluation chip. Consequently, a cost, time, etc., associated with designing can be reduced since re-designing of the evaluation chip is unnecessitated only by newly providing the peripheral circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer suitable for use as an evaluation chip or the like.

[0002]

2. Description of the Related Art A microcomputer reads a program instruction from a memory, and executes a setting operation of constituent elements, various logical operation operations, and the like according to a result of decoding the program instruction by an instruction decoder. Generally, the wiring of the instruction decoder is fixed using a logic circuit such as a PLA.

[0003]

For example, when the microcomputer is an evaluation chip, if a peripheral circuit is added or changed in the course of developing a program, the peripheral circuit can be handled by an external circuit of the chip. The instruction code for controlling the circuit cannot be added or changed because the wiring of the instruction decoder is fixed. Therefore, it is necessary to redesign the evaluation chip, and there is a problem that the design cost is high and the design time is long.

Accordingly, an object of the present invention is to provide a microcomputer which can share the evaluation chip for a plurality of uses.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems. The present invention decodes a program instruction read from a program memory, and performs a setting operation of constituent elements and a logical operation. And the like, in which all or a part of an instruction decoder for decoding a program instruction is constituted by a flash memory. The flash memory is characterized in that the program instruction is supplied as address data. Further, the flash memory includes a PLA that constitutes the instruction decoder.
Has the same bit length as the number of output lines.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a microcomputer according to the present invention.

In FIG. 1, a ROM (1) stores program instructions for setting constituent elements of a microcomputer to a specific state or performing a specific logical operation on external data. . In the case of a one-chip microcomputer for mass production, the ROM (1) is constituted by a non-volatile memory such as a mask or a flash and is built in. In the case of an evaluation chip, the ROM (1) is a volatile memory such as an SRAM. And provided independently outside.
This is a so-called program RAM. The word length of the ROM (1) is m bits. Program counter PC (2)
Is used to address the ROM (1), and is set to address 0 when the microcomputer is initialized, and then its value is incremented or jumped according to the result of decoding the program instruction in the ROM (1). Instruction register IR (3) is ROM
It holds the program instructions, table information, etc. read from (1). The RAM (4) is a volatile memory such as an SRAM, and writes and reads operation processing data. Data pointer (5) is RAM
The address (4) is designated, and the table information held in the instruction register (3) is set as address data via the internal bus (6). Arithmetic logic unit ALU (7) is ROM
(1) or internal data read from RAM (4),
ROM (1) for external data supplied from outside
And executes logical operation processing according to the result of decoding the program instruction. The operation processing result of the operation logic unit (7) is written to the RAM (4) via, for example, the internal bus (6).

[0009] The instruction decoder (8)
It is composed of an LA section (8a) and a flash memory section (8b), and is stored in the instruction register (3).
It decodes a bit program instruction and outputs a control signal. That is, the PLA unit (8a) and the flash memory unit (8b) convert m inputs into n outputs. The PLA section (8a) arranges m signal lines and n signal lines vertically and horizontally and connects predetermined intersections, and has a fixed one-to-one input / output relationship between m inputs and n outputs. It is the one that has. Therefore, when an m-bit program instruction is supplied to the PLA unit (8a), n control signals are output from the PLA unit (8a). The n control signals are used to set the state of components inside the microcomputer and to set the state of external peripheral circuits. The flash memory unit (8b) is a nonvolatile memory capable of batch electric erasure of data and writing / reading of data. The flash memory unit (8b) is supplied with an m-bit program instruction as address data, and transmits an n-bit control signal from an address designated. Output. Therefore, a control signal (n-bit binary data) according to the specification of the microcomputer is written in the flash memory unit (8b) in advance.
The contents of the instruction register (3) are P
Although supplied to both the LA section (8a) and the flash memory section (8b), the instruction register (3)
Is stored in the flash memory unit (8b), the address is not specified, and no control signal is output from the flash memory unit (8b). On the other hand, if the content held in the instruction register (3) is a value designating the flash memory unit (8b), no control signal is output from the PLA unit (8a). The ratio of the flash memory unit (8b) to the instruction decoder (8) is as follows:
Depending on the application, it may be all or part.

As described above, since the contents of all or a part of the instruction decoder (8) can be changed, when a program evaluation is performed using an evaluation chip, the peripherals are changed along with the change or addition of the specification (program) of the microcomputer. Even when the circuit needs to be changed or added, the instruction code can be easily changed only by rewriting the contents of the flash memory (8b) constituting the instruction decoder (8). Since the flash memory (8b) can be rewritten collectively, the rewriting time is short. Therefore,
It is not necessary to redesign the evaluation chip, and it is possible to reliably prevent the problems that have been encountered in the past.

[0011]

According to the present invention, since all or a part of the contents of the instruction decoder can be changed, when a program evaluation is performed by an evaluation chip, the peripheral circuit is changed in accordance with a change or addition of a microcomputer specification. Even when it is necessary to change or add the instruction code, the instruction code can be easily changed only by rewriting the contents of the nonvolatile memory constituting the instruction decoder. Therefore, an advantage that redesign of the evaluation chip becomes unnecessary is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer of the present invention.

[Explanation of symbols]

 (1) ROM (8) Instruction decoder (8b) Flash memory

Claims (4)

[Claims] 1. A microcomputer that decodes a program instruction read from a program memory and executes a setting operation of a constituent element, a logical operation operation, and the like. Characterized by comprising an electrically rewritable nonvolatile memory. 2. The microcomputer according to claim 1, wherein the non-volatile memory is supplied with the program instruction as address data. 3. The nonvolatile memory according to claim 2, wherein each word of the nonvolatile memory has the same bit length as the number of output lines of a PLA constituting the instruction decoder.
The microcomputer as described. 4. The microcomputer according to claim 1, wherein said nonvolatile memory is a flash memory.