JPS6284365A - Program developing device - Google Patents

Abstract

PURPOSE:To set optionally a function of a PLA through the changeover of internal wiring only at the development of a microcomputer (MCP) by controlling a gate provided at a cross point of input/output lines corresponding to the those of the PLA of the MCP incorporating the PLA. CONSTITUTION:In order to change a PLA data partially at the program development based on the predetermined PLA data in a memory 5, the location to be changed is commanded to a control circuit 4. The circuit 4forms a data to turn on/off a transmission gate 8 instructed and the data is to be written in a corresponding latch circuit 3 only and the operation by the change is to be confirmed. After the confirmation of operation, the PLA data is written in the memory 5 and it is used to form a mask at the manufacture of a MCP.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a program development device for a microcomputer incorporating a PLA, and particularly relates to an improvement in the wiring of a PLA provided in the program development device.

(b) Conventional technology In general, one-chip microcomputers have a built-in ROM (read-only memory) for storing programs, and programs created by the user etc. are written in using a mask during manufacture of the one-chip microcomputer. It will be done.

Therefore, when creating a program, users use a program development device using a microcomputer called an evaluation chip.

By the way, some one-chip microcomputers have a built-in PLA (programmable logic array) that can be freely programmed according to the user's requests. For example, a display device with a built-in driving circuit or the like has a built-in segment PLA for displaying data. B's PLA can also be freely set by the user during program development, so when manufacturing a one-chip microcomputer, the PLA address and the data to be written to that address are required.

Conventionally, when programming a PLA in a program development device, a PLA built in a microcomputer is used.
Use the E F ROM for PI and A instead of
Data created in advance was written to FROM. This is described on pages 31 to 37 of ``Microcomputer Material Series Yang 3'LM6499 Manual'' published by the applicant on February 15, 1980.

(c) Problems to be solved by the invention However, when a PLA is created using an EPROM as in the past, even if some of the contents of the PLA are changed during program creation, all memories are lost. This was inconvenient because it had to be erased and rewritten. Furthermore, if the number of input lines or output lines increases, the EPROM cannot handle it. On the other hand, there are cases where a PLA is created by wiring input lines and output lines one by one without using EFROM, but in this case, some changes require only a partial change. This can be done, but it takes time to wire each wire one by one, and wiring errors may occur.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned points, and includes input lines and output lines corresponding to the input lines and output lines of the PLA of a microcomputer, and A gate provided at each intersection of a line and an output line, a decoder circuit that individually controls each gate, and a latch circuit that applies data representing on and off of each gate to the decoder circuit. By applying wiring data of the created PLA to the latch circuit, a PLA equivalent to a microcomputer is created.

(*) Effect: According to the above-mentioned means, the PLA setting data set at the time of creating the microcomputer program can be stored in the storage device (
For example, magnetic disk, RAM.

The setting data read out from the storage device is subjected to predetermined processing and applied to a latch circuit for storage. Then, the output of the latch circuit is converted by the decoder circuit into a control signal for turning on or off each gate, and the desired gates are turned on or off to form the set PLA.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
) is the logic array section, (2) is the decoder circuit, (3)
is a latch circuit, (4) is a control circuit, and (5) is a P
This is a storage device that stores LA data.

The logic array section (1) is provided with one input line (6) and one output line (7) orthogonal to each other,
A gate (8) is connected to each of the intersection points. Each gate (8) is turned on and off by a decoder circuit (2).
) is controlled by the output from One decoder circuit (2) corresponds to each output line (7), and there are n decoder circuits in total. Each decoder (2) also has an input line (6).
The number of launch circuits (2) equal to the number of bits of the binary number representing the number m of lines is provided. Control circuit (4
) is created by a microcomputer, for example, reads PLA data stored in the storage device (5) and other PLA data representing the internal settings of the one-chip microcomputer, performs arithmetic processing, and stores the gate (
8) is created and sequentially stored in the latch circuit (3>).

Next, FIG. 2 shows a specific circuit when there are eight input lines (6). In the logic array section (1), transmission gates (9) are connected to the intersections of eight input lines (6) and one output line (7), respectively, and are connected to one output line (7). The control input of the transmission gate (9) is N, which constitutes the decoder circuit (2).
Each is connected to the output of an AND gate (10). This decoder circuit (10) selectively connects the Q and Q outputs of each of the three launch circuits (3) to eight NAND gates (10).
According to the contents of the binary data stored in the three latch circuits (3), eight NAND
The output of only one of the gates (10) is “0”
'. In addition, the inputs of the three latch circuits (3) corresponding to each decoder 2) are data inputs, ,D, ,D,
Furthermore, strobe signals φ1, φ, . . . are connected to the clock input signal φ, respectively.
φ0 is applied. For data inputs D1, D2, D,
Clock signals φ1, φ2・from the control circuit (4)
...φ. and a transmission gate (9) connected to the output line (7) of the logic array (1).
) is input, indicating the position where the switch is turned on.

For example, if the data read out from the storage device (5) by the control circuit (4) is "101" and this data is stored in the first latch circuit (3) at the timing of the clock signal φ1, the decoder circuit As for the output of (2), only the output G6 of the sixth NAND gate (10) becomes "0'', so the transmission gate <9) to which the output G6 is applied turns on. Therefore, the input line (6) The applied signal IN can be output to the output OUT.Similarly, the clock signals φ2, φ, . . .
...φ. When data is stored in each of the latch circuits (3), one of the transmission gates (9) of each output line (7) is turned on, and one of the input signals IN1 to INF is output to the output OU". r, ~OUT,
Selectively output.

By the way, when the program development device is operated based on PLA data predetermined in the storage device (5), if for some reason you want to convert a part of the PLA data, you can instruct the control circuit (4) where to change the data. Then, the control circuit (4) generates data for turning on or off the specified transmission gate (9), and the corresponding latch circuit (3)
It is now possible to write data only to
You can check the behavior of the changes. After confirming the operation, the PLA data is written into the storage device (5) again and used for creating a mask when manufacturing a microcomputer.

(g) Effects of the invention As described above, according to the present invention, the microcomputer P
Wiring errors when creating a PLA of a program development device corresponding to an LA are eliminated, and the PLA can be created easily. Furthermore, it is easy to make partial changes, and program development and PLA development can be carried out in a short period of time, which has the advantage of shortening the period from receiving an order to producing and shipping a microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific circuit of the block shown in FIG. Explanation of main drawing numbers (1)...Logic array section, (2)...Decoder circuit, (3)...Latch circuit, (4)...Control circuit, (5)...Memory device, (6)...
Input line, (7)...output line, (8)...gate.

Claims (1)

[Claims] 1. ROM that stores programs (read-only)
PLA (memory) and PLA (memory) that creates predetermined data from data.
In a microcomputer program development device having a programmable logic array (programmable logic array) on one chip, an input line and an output line corresponding to the input line and output line of the PLA, and an intersecting point of the input line and the output line, respectively. The PLA created has a gate provided, a decoder circuit that separately controls each gate, and a latch circuit that applies data representing on and off of each gate to the decoder circuit. 1. A program development device, wherein a PLA equivalent to the microcomputer is created by applying wiring data of the above to the latch circuit.