JPS61276046A - Data processor with memory diagnostic function - Google Patents

Abstract

PURPOSE:To shorten the memory diagnostic time by writing the same data in all banks simultaneously in the diagnostic mode and writing and reading data on and from the memory bank designated by an address in the normal mode. CONSTITUTION:When a memory diagnostic program is executed, a FF 5 is set; and in case that data is written on an address of a bank 4A, a write-enable signal WR, a select signal SA, an AND circuit 6, and OR circuits 7-9 are set to '1' together. Consequently, write data on a data bus 3 is written on individual banks simultaneously. In case of data read of the bank 4A, the signal WR is set to '0', and the AND circuit 6, select signals SB-SD, and OR circuits 7-9 are set to '0' also, and only the select signal SA is '1'. Consequently, only data of the bank 4A is read out and is diagnosed. Following banks are diagnosed similarly. When the FF 5 is reset to set the normal mode, the AND circuit 6 outputs always '0', and select signals SA-SD are inputted to banks 4A-4D to read and write memory contents in 1:1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a data processing device with a memory diagnostic function.

[Conventional technology]

Conventionally, memory diagnosis of a data processing device has been performed by writing and reading data into a memory for every l address, and comparing these two pieces of data.

[Problem that the invention seeks to solve]

Since the above-described conventional memory diagnosis method diagnoses every l address, it has the disadvantage that it takes time to diagnose a large capacity memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device with a memory diagnostic function that reduces memory diagnostic time.

[Means for solving problems]

The present invention configures the storage unit to consist of a plurality of memory banks, and when writing data to the memory during the memory diagnostic mode, the same data is simultaneously written to all memory banks, and when writing data during other normal modes. When reading data, by writing and reading data only to the memory puncture specified by the address bus,
This is intended to shorten memory diagnosis time.

That is, the data processing device with a memory diagnostic function of the present invention includes a storage unit including a plurality of memory banks, a mode setting circuit that outputs a mode signal indicating a diagnostic mode or a normal mode, and a mode setting circuit that outputs a mode signal indicating a diagnostic mode or a normal mode. A method for simultaneously writing data to all memory banks when writing data to the storage unit, and a means for writing data to multiple memory banks when writing data to the storage unit when the mode signal is the normal mode. A means for writing data into only one of the banks, and a means for reading data from this storage section,
Regardless of the mode signal.

It has means for reading data only from any one of the plurality of memory banks.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a data processing apparatus according to the present invention.

The storage section is composed of four readable/writable memory banks 4A, 48.4G, and 4D each consisting of eight memory chips (16 bits/chip). Address assignments for each memory bank 4A, 4B, 4C, and 4D are 00001 to 3FFFN, 400, respectively.
0H~7FFFH, 80008NBFFF)l, C
00On "FFFFH.The decoder 2 inputs the address from the address bus 1, and outputs the address converted into an address in the memory bank to each memory bank 4A, 4B, 4C, and 4D (not shown), and also outputs the address (not shown). Decode the upper 4 bits and write each memory bank 4A.
, 48.40.40 are selected or not.

Outputs Sc and S ports. Flip-flop 5 is CP
A set signal is input from U (diagnostic program) in the diagnostic mode, and a reset signal is input in the normal mode, and signals of "1" and "O" are output from the Q terminal, respectively. AND circuit 6
are the puncture select signal S^ and the write enable signal WR.
and the output of the flip-flop 5. The OR circuit 7 takes the logical sum of the output of the AND circuit 6 and the bank select signal SR, and outputs a signal for selecting the memory bank 4B. The OR circuit 8 takes the logical sum of the output of the AND circuit 6 and the bank select signal Sc, and outputs a signal for selecting the memory bank 4C. The OR circuit 9 takes the logical sum of the output of the AND circuit 6 and the puncture select signal S, and outputs the output of the memory bank 4.
A signal for selecting D is output.

Next, the operation of this embodiment will be explained.

(1) When the memory diagnostic program is executed, the flip 20 knob 5 is first set and 1° is output from the Q terminal. And the memory diagnostic program is memory bank 4
When writing data 00)1 to address 0000M of A, first the write enable signal WR becomes "l", the bank select signal S^ to the memory bank 4A also becomes "l", and at this time the output of the flip-flop 5 becomes "1". ”, the output of the AND circuit 6 is “1”.
Since the output of is the input of OR circuit 7, 8.9,
The outputs of these OR circuits 7, 8.9 also become "1", and memory banks 48, 40, 41 are selected together with memory bank 4A. Therefore, when write data 0ON is output to the data bus 3, the address 0OOOH of the memory bank 4A and the address 4000M of the memory bank 4B, which is the start address of each memory bank 48.4C, 40, are output.
, data OOo are simultaneously written to address 8000M of memory bank 4C and address COOOH of memory bank 4D.

Next, when reading the data at address 0000H of memory bank 4A, first the write enable signal WR is set to “O”.
Therefore, the output of the AND circuit 6 becomes "O". Also,
Bank select signal S^ output from decoder 2,
Among Svs, Sc, and So, the signal S^ is “1pa,
Signal S! Since 1, Sc, and So are "0", the output of the OR circuits 7, 8.9 becomes "O". therefore,
Only data 00M at address 0000H of memory bank 4A is read out from the storage section, and the diagnosis for address 0000H of memory bank 4A is completed.

Furthermore, address 400fin of memory bank 4B,
Data at address 8000M of memory puncture 4C and data at address CQOOH of memory puncture 4D are similarly read and diagnosed.

Then, by changing the write data to OOH=FFn and performing diagnosis, address 0000840008
, 8000M, the diagnosis of the GOOOn memory is completed, and the write address to the memory bank is set to 0.
All memory diagnosis is completed by changing the data from 0001 to 3FFFM and comparing the data up to the write address 0000M=FFFFu.

(2) Finally, when flip-flop 5 is reset (normal mode), the output of AND circuit 6 is always “θ”
Therefore, the puncture select signal S^ outputted from the decoder 2 is sent as is, and the outputs Ss, Sc, and 5 are sent to the memory bank 4A through the OR circuits 7, 8, and 9.

48, 4G, and 4D. Therefore, in this case, the contents of the memory corresponding to the address on a one-to-one basis can be read and written.

〔Effect of the invention〕

As described above, the present invention has the effect of shortening the memory diagnosis time by providing the memory with a memory puncture configuration and simultaneously writing data to the memory bank during memory diagnosis.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of a data processing device with a memory diagnostic function according to the present invention. WR...Write enable signal 4A, 4B, 4G, 40...Memory bank 5.
...Flip-flop 6...AND circuit 7.8.9...OR circuit S^, SB, Sc, So...Punk select signal Patent applicant NEC Corporation B+rV, ""

Claims (1)

[Scope of Claims] A storage section including a plurality of memory banks; a mode setting circuit that outputs a mode signal indicating a diagnostic mode or a normal mode; and a mode setting circuit that outputs data to the storage section when the mode signal is a diagnostic mode. means for writing data into all memory banks at the same time when writing data; and means for writing data into all memory banks at the same time when writing data into the storage section when the mode signal is the normal mode; and means for reading data from only one of the plurality of memory banks, regardless of the mode signal, when reading data from the storage section. A data processing device with a memory diagnostic function.