JPS59173868A - Address control system - Google Patents

Abstract

PURPOSE:To facilitate control of addresses for input and output by constituting a buffer memory with plural chips in response to the address and selecting these chips. CONSTITUTION:A decoder 1 decodes addresses A11-A13 among access addresses A0-A15 which are given to a buffer memory and accordingly delivers selectively the chip selection signal CS to memory chips 2-4 constituting a data memory of the buffer memory from AND circuits 7-9. These chips 2-4 to which data are set among buffer memories constitute a buffer memory together with memory chips 5 and 6.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention particularly relates to an address control method for a buffer memory with a capacity of 6. A system that has address counters and inputs data to the values of these counters,
The present invention relates to an address control method that assumes a memory space of 12 times 6 when controlling data output, and facilitates calculation of the difference between an input address and an output address.

[Technical background, prior art, and problems thereof] For example, when reading/writing data to a magnetic disk device, a buffer memory is provided in the magnetic disk control device, and the read/write data is temporarily stored in the buffer memory. Fill out. At this time, the buffer memory is FiFo (First-in-s
used in a first-of-its-kind manner.

By the way, the capacity of this buffer memory is 2K.

4, 8, 16K, etc. 2n
With this configuration, even if we assume double space, the input address can access the buffer memory by looking at only the lower bits of the size 2n, so it is possible to access the buffer memory without considering the most significant bit. There is no need to do anything special with the address or chip select. therefore,
Conventionally, even when a double space was assumed using a buffer memory with a capacity of 2n, there was no need for a special circuit configuration for the address and chip select.

However, due to mounting restrictions or the convenience of a two-circuit configuration, it may be necessary to use a buffer memory with a small capacity. Then.

The buffer is created using only the lower bits, ignoring the upper bits.
Memory cannot be accessed.

[Purpose of the invention]

An object of the present invention is to improve such problems and to facilitate the management of input/output addresses using a specific number of lower bits even when using a buffer memory having 6K (D addresses). In this case, the address space is reduced to 2 to 6 real capacity.
An object of the present invention is to provide an address control method that converts a virtual address into a real address necessary for accessing a buffer memory even when the number of addresses is doubled to 12K.

[Structure of the invention]

In order to achieve this object, the address control method of the present invention has two address counters for data input and an address counter for data output.
After inputting data to the above buffer memory, this buffer
In the memory circuit which is used to output when the memory is vacant, the buffer number memory is constituted by a plurality of chips according to addresses, and a chip select generation means is provided for selecting these chips.

The upper specific bits of the input address counter are coded by the chip select generation means to select a specific chip, and the actual address space is determined by the selected chip and the lower bits of the input address counter. It is characterized by the following.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 112 and 3.

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram illustrating a memory configuration, and FIG. 3 is a diagram illustrating an address.

In the figure, 1 is a decoder, 2 to 4 are memory chips for 2'K x 8 pit data, 5 and 6 are memory chips for 4 x 1 bit parity, 7 to 9 are AND circuits, 1
0.11 is a NAND circuit, and 12°13 is an inverter.

Decoder 1 selects All, Ala, and A among the access addresses AO to A15 to the buffer memory.
A chip select signal C8 is sent to the memory chips 2.3 and 4 which selectively configure the data memory of the buffer memory by decoding the address of 13 and selectively using AND circuits 7 to 9 accordingly. This outputs the following.

Memory chips 2 to 4 are the ones in the buffer memory in which data is set, and constitute the buffer memory together with the parity memory chip 59.6.

The buffer memory is configured as shown in FIG.

This buffer memory is composed of data memory chips 2 to 4 in which data is written and parity memory chips 5 to 6 in which parity bits are written. Chip 2 has a real address of 01 (
It must be in the range -1.

Memory chip 3 for data has a real address of 2″~3
Memory chip 4 has real addresses in the range 4 to 5. The parity memory chip 5 has real addresses in the range OK to 3, and the memory chip 6 has real addresses in the range 4 to 5.

In the present invention, for input addresses, the capacity of the sofa memory is 12 bytes, which is twice that.
As shown by the dotted line in Figure 2, the range of -BK is assumed to be 6. Then, the virtual address of -BK is assigned to each memory chip as shown by the solid line in Figure 2. That is, for input address 6 to 7K, write to memory chip 2, for input address 8 to 9K, write to memory chip 3, and for AK-BK, write to memory chip 2. Similarly, for parity pits, 6 to 9K are written to memory chip 5, and AK-BK are written to memory chip 6.

By the way, the memory chips 2, 3, and 4 have a capacity of <2 bytes as described above, and as shown in FIG.

AO-Alo 4 teno 11 bits can indicate the address management.

And the address of 3 pins from All to A13)
K~IK, 2~3, 4~5Kl ol(~'i'
, to 8) (to 9), it is possible to decipher the range AK-BK. In this case, as above, <6 to 7 is OK to I
As in the case of K, specify memory chip 2 and select
K to 9 specifies memory chip 3 in the same way as 2 to 3, and AK-BK specifies memory chip 4 in the same way as 4 to 5.

Therefore, all of the address signals in the decoder 1 are
Decipher A13 and use AND circuits 7.8, 9 accordingly.
Selective memory chips 2, 3, and 4
By outputting the select signal C8 and accessing the address area specified by the lower 11 bits AO to AIO of the address signal for the memory chip specified by the chip select signal C8, the memory chip specified by the chip select signal C8 is accessed. area can be accessed. Thus, the virtual address space of 6-BK is necessarily converted to the address space of OK-5.

In FIG. 1, the gate signal is output as "1", so when memory chip 2 or 3 is selected, AND circuit 9 outputs "0", so inverter 13 outputs "0". 1'', and the NAND circuit 11 outputs l'-
OJ is output, but the NAND circuit 10 outputs "1" and the chip select signal C8 selects the memory chip 5.
will be applied. When memory chip 4 is selected, "1" is output from AND circuit 9, so NAND circuit 11 outputs "1" and memory chip 6 is selected. At this time, the NAND circuit lo outputs "o", so the memory chip 5 becomes non-selected.

In FIG. 1, address signals AO to A16 and gate signals are output from a DMAC (direct memory access control device) not shown.

Data is sent out on a data bus (not shown).

And when the input address is the CK address.

Since the output address always exceeds 6K, at this point, 6K is subtracted from the input address and output address to return to the real address.

Note 1: In the present invention, the reason for preparing an address space twice as much as the real address space for t6 is that the address cannot be changed to a real address while exceeding the boundary of t6, and also because the input address exceeds 6K. This is because if the real address is changed from zero at this point, it will be difficult to calculate the address difference.

Moreover, when the number exceeds 6K, the parity memory is also converted to the memory chip 5 for OK to 3. Therefore, in reality, the second half of the second half of the parity memory chip 6 is not used.

In the present invention, it is noted that when a buffer memory with a capacity of 6 is used in a FIFO manner, the difference between the input address and the output address will never be more than 6. For example, if the output address is 0. Then, the input address will be 5FFF and will never be 6000. This is due to the fact that the buffer memory is 6), and by assuming a space twice this (12) (for example, if the output address is 5FFF, the input address is BFFE, and the actual address is 5FFE), the input/output address difference calculation can be facilitated. If the address difference calculation is performed using the real address, 5FFF - 5FFF, the answer will be a negative value, so calculating the address difference will not be easy, but calculating BFFE - 5FFF will be easy because the answer will be positive.

〔Effect of the invention〕

, according to the present invention, the buffer memory of 6 is FiF.

Address management for input and output can be made easier when used as in . Therefore, when using an 8-sized buffer memory configured using 4 2-sized memory chips, the cost can be lowered, and the mounting space of the memory chips can also be slightly saved. .

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram illustrating a memory configuration, and FIG. 3 is a diagram illustrating an address. In the figure, 1 is a decoder, 2 to 4 are memory chips for data, 5 and 6 are memory chips for parity, 7 to 9 are AND circuits, 10 and 11 are NAND circuits, and 12 and 13 are inverters. . Patent applicant Fujitsu Limited

Claims (1)

[Scope of Claims] An address counter for data input, an address counter for data output, and a buffer memory are provided, and data is manually input to the buffer memory and then output when the buffer memory is free. In memory circuits designed for use in The buffer memory is configured with a plurality of chips according to addresses, and a chip select generation means is provided for selecting these chips, and the upper specific bit of the input address Φ counter is coded by the chip select generation means. An address control method characterized in that a specific chip is selected and a real address space is determined by the selected chip and the lower bits of the input address counter.