JPH0219921A - First-in/first-out memory - Google Patents

Abstract

PURPOSE:To confirm the normal state of a memory array by writing the check data added with a parity bit into a memory and reading out the data to perform the parity check. CONSTITUTION:The check data outputted from a check data production circuit 9 is inputted to a parity generator 11 from a selector 10 and written into the address of a memory array 6 designated by a write address pointer 5 after receiving a parity bit. Then the data is read out of the array 6 based on the designation of an address done by a read address pointer 7 and then inputted to a parity checker 12. The checker 12 performs the parity check of the data and outputs a parity check signal 110 showing the result the parity check. A write/read control circuit 13 checks the signal 110 and outputs a parity error signal 109 when a parity error is detected. As a result, the normal state of the memory array can be checked even in a data memory state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a first-in first-out memory (hereinafter abbreviated as FIFO memory).

[Conventional technology]

A conventional FIFO memory will be explained using FIG. 2.

When the write signal 102 is input to the write control circuit 21, the write control circuit 21 generates a data launch signal and outputs it to the input buffer 22. As a result, the input buffer 22 latches the write data 101 that is being input at that time, and outputs the latched write data to the memory array 26. The write control circuit 21 also outputs a write address count-up instruction signal to the write address pointer 25. As a result, the write address pointer 25 counts up the write address and provides a write signal together with new write address information to the memory array 26. As a result, memory array 2
6 writes data from the buffer 22 to the address specified by the pointer 25.

On the other hand, when the read signal 106 is input to the read control circuit 24, the control circuit 24 outputs a successive address count up instruction signal to the successive address pointer 27. As a result, the successive address pointer 27 counts up the successive address, and provides the new successive address information and a successive signal to the memory array 26.

As a result, the memory array 26 reads out the data specified by the pointer 27 and outputs it to the output buffer 23.

Control circuit 24 also generates a data launch signal and outputs it to output buffer 23. As a result, data from the memory array 26 is latched into the output buffer 23 and then output as subsequent data 105.

The flag control circuit 28 counts the data latch signals output from the control circuits 21 and 24, and counts the number of data written in the memory array 26 and the memory array 2.
The number of data read from 6 is constantly compared to monitor whether the memory array 26 is full of data or whether no data is stored in the memory array 26 (data empty state). When the data is full, a data full flag 104 is output, and when the data is empty, an empty flag 107 is output.

Note that when the reset signal 103 is input, the pointers 25 and 27 are reset, and each outputs an initial address.

When checking the normality of such a conventional FIFO memory, for example, write data with a parity bit added is stored in the memory array 26, and then read from the memory array 26. At that time, a parity check was being performed on that data, that is, the successive data 105.

[Problem to be solved by the invention]

Therefore, in the conventional FIFO memory, the normality of the memory array can be confirmed only when, for example, write data with a parity bit added is stored in the memory array 26 and is read from the memory array 26. However, it was impossible to check the normality when the data was empty.

The purpose of the present invention is to eliminate such drawbacks and to provide an F that can check the health of the memory array even when data is empty.
The purpose is to provide IFO memory.

[Means to solve the problem]

The FIFO memory of the present invention includes a data creation circuit that generates check data, and a data creation circuit that selects and outputs either the check data generated by the data creation circuit or data to be written to the memory based on a predetermined control signal. a selector; a parity generator that adds a parity bit to the data output by the selector and outputs it to the memory; a parity checker that performs a parity check on the data read from the memory; and a parity checker that performs a parity check on the data read from the memory; a flag control circuit that outputs a predetermined flag signal when the check data is not selected; and a flag control circuit that outputs the control signal to cause the selector to select the check data when the flag control circuit outputs the flag signal; and a control circuit that instructs the memory to write data output from the memory and read data output from the memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a FIFO memory according to the present invention. The write control circuit 1 receives a write signal 102
is input, the data latch signal is input to buffer 2.
and a write address count-up instruction signal to the write address pointer 5, and a write notification signal to the write/continuation control circuit 13, respectively.

When the write/continuation control circuit 13 receives the write notification signal, it outputs a control signal to the selector 10 to select data from the input cover sofa 2.

When input buffer 2 receives the data launch signal, it latches write data 101 and outputs it to selector 10 . The selector 10 operates based on a control signal from the control circuit 13, selects data from the large power buffer 2 or the check data generation circuit a, and selects the data from the large power buffer 2 or the check data generation circuit a to be sent to the parity generator 1.
Output to 1. Parity generator 11 is selector 1
A parity bit is added to the data starting from 0 and output to the memory array 6.

The write address pointer 5 counts up the write address when the instruction signal is input, and provides a write signal to the memory array 6 together with new write address information.

Further, when the reset signal 103 is input, the address given to the memory array 6 is reset and set to the initial address.

When the read signal 106 is input to the successive output control circuit 4,
Data latch signal output buffer 3 and flag control circuit 8
Then, a successive address count-up instruction signal is output to the successive address pointer 7, respectively.

When the successive address pointer 7 receives a successive address count-up instruction signal, it counts up the successive address and supplies the successive address signal to the memory array 6 together with new successive address information. Further, when the reset signal 103 is input, the address given to the memory array 6 is reset and set to the initial address. The parity checker 12 performs a parity check on the data read from the memory array 6, and a parity check signal 11 representing the result.
0 is output to the control circuit 13. When the data latch signal is input, the output buffer 3 latches the data from the parity checker 7 and 12 and outputs it as successive data 105.

Flag control circuit 8 counts each data latch signal output by control circuit 1.4, constantly compares the number of data written to memory array 6 and the number of data read from memory array 6, and It is monitored whether the array 6 is full of data or whether no data is stored in the memory array 6 (data empty state).

When the data is full, the data full flag 104 is output, and when the data is empty, the empty flag 10 is output.
Outputs 7. For example, if there is still space, the data full flag 104 is set to logic "0", and if it is full, it is set to logic "1". Furthermore, if data is stored, the empty flag 107 is set to logic "0", and if it is in an empty state, it is set to logic "1". By outputting such a flag signal, the next write is prohibited when the memory is full, and when the read signal 106 is input in the empty state, it is indicated that no data exists.

The write/continuation control circuit 13 outputs a clock signal 108 when the flag control circuit 8 outputs the empty flag 107.
When a predetermined time has elapsed, the check data creation circuit 9 is instructed to create check data in order to write and read check data, and a control signal is output to the selector 10 to cause the check data creation circuit 9 to write and read the check data. Select data from. The control circuit 13 also instructs the write address pointer 5 to count the write address and causes the write signal to be output to the memory array 6 together with the new write address. Control circuit 13 subsequently instructs successive address pointer 7 to count up the address, and outputs a successive signal to memory array 6 together with a new successive address. Furthermore, the control circuit 13 examines the parity check signal 110 from the parity checker 12,
Parity error signal 10 if there is a parity error
Outputs 9. The control circuit 13 repeats this operation until the write notification signal is input from the control circuit 1.

Next, the write operation will be explained. When the write signal 102 is input, the write control circuit l outputs a write notification signal to the write/continuation control circuit 13. As a result, the write/continuation control circuit 13 outputs a control signal to the selector 10 to select data from the high-power buffer 2. The write control plane 1 also outputs a data latch signal to the input buffer 2 when the write signal 102 is input, causing the write data 101 input at this time to be latched. This latched write data is input to the parity generator 11, where a parity bit is added, and then output to the memory array 6.

The write control circuit 1 also outputs a write address count-up instruction signal to the write address pointer 5 when the write signal 102 is input. As a result, the write address pointer 5 counts up the write address and provides a write signal to the memory array 6 along with new write address information. As a result, memory array 6 specified by pointer 5
Data from the parity generator 11 is written to the address.

Next, the read operation will be explained. When the continuation signal 106 is input, the continuation control circuit 4 outputs a continuation address count up instruction signal to the continuation address pointer 7. The successive address pointer 7 thereby counts up the successive address and supplies a successive signal to the memory array 6 together with new successive address information. The memory array 6 reads the data at the given address, and the parity
Output to 2. Parity checker 12 is memory array 6
A parity check is performed on the data read from the , and a parity check signal 110 representing the result is output.

The control circuit 13 checks this signal and outputs a parity error signal 109 if there is an error.

Also, since a data latch signal is input from the control circuit 4 to the output cover sofa 3 at this time, the data from the parity checker 12 is latched and outputted as successive data 105.

Next, operations related to flag control will be explained.

The flag control circuit 8 controls the memory array 6 by counting the data latch signals output by the control circuits 1 and 4 during the write or read operation described above.
The number of data written to the memory array 6 is constantly compared with the number of data read from the memory array 6 to monitor whether the memory array 6 is full of data or empty. . When the data is full, a data full flag 104 of logic "1" is output,
When the data is empty, an empty flag 107 of logic "1" is output.

Next, the normality check operation in the empty state will be explained. When the flag control circuit 8 outputs the empty flag 107 with logic "1", the write/continuation control circuit 13 counts the clock signal 108 and determines that the empty state continues after a predetermined period of time has elapsed. do. Then, in order to write and read check data, the check data creation circuit 9 is instructed to create check data, and a control signal is output to the selector 10 to select data from the check data creation circuit 9. Control circuit 13 also instructs write address pointer 5 to count up the write address, and outputs a write signal to memory array 6 together with a new write address. The control circuit 13 then instructs the successive address pointer 7 to count up the successive address, and outputs the successive address signal to the memory array 6 together with the new successive address.

Through this operation, the control circuit 13 inputs the check data output from the check data generation circuit 9 to the parity generator 11 from the selector 10, adds a parity bit there, and then converts it to the address of the memory array 6 specified by the pointer 5. will be written to. This data is read out from memory array 6 based on the addressing of pointer 7 and input to parity checker 12. Parity checker 12 performs a parity check on this data and outputs a parity check signal 110 representing the result. The control circuit 13 uses this parity check signal 110
is checked, and if there is a parity error, a parity error signal 109 is output.

The control circuit 13 maintains this state until the write notification signal is input from the control circuit 1, and during that time it sequentially accesses the addresses of the memory array 6 and outputs a parity error signal 109 if there is an abnormality.

When the write notification signal is input from the control circuit 1, the control circuit 13 finishes the normality check operation, resets the pointers 5 and 7 and the check data creation circuit 9, and
The selector 10 is set to select data from the input sofa 2. Thereafter, writing of the data 101 described above is performed under the control of the control circuit 1.

〔Effect of the invention〕

As explained above, the FIFO memory of the present invention includes a data creation circuit that generates check data, and a data creation circuit that generates either check data or write data to memory based on a predetermined control signal. A selector that selects and outputs data, a parity generator that adds a parity bit to the data output by this selector and outputs it to the memory, a parity checker that performs a parity check on the data read from the memory, and a parity checker that performs a parity check on the data read from the memory. A flag control circuit outputs a predetermined flag signal when no data is stored, and when this flag control circuit outputs the flag signal, outputs a control signal to cause the selector to select the check data, and a parity generator. and a control circuit for instructing the memory to write data output from the memory and read data output from the memory.

Therefore, in the FIFO memory of the present invention, even when data is empty, the normality of the memory array can be confirmed by writing check data with a parity bit added to the memory, and then reading that data from the memory and performing a parity check. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a FIFO memory according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional FIFO memory. 1...Write control circuit 2...Input cover sofa 3...Output cover sofa 4...Continuation control circuit 5...Write address pointer 6...・Memory array 7... Successive address pointer 8... Flag control circuit 9... Check data creation circuit 10... Selector 11... Parity generator 12... ...Parity checker 13...Write/read control circuit

Claims (1)

[Claims] (1) a data generation circuit that generates check data; a selector that selects and outputs either the check data generated by the data generation circuit or data written to memory based on a predetermined control signal; a parity generator that adds a parity bit to the data output by the selector and outputs it to the memory; a parity checker that performs a parity check on the data read from the memory; and a parity checker that performs a parity check on the data read from the memory; a flag control circuit that outputs a predetermined flag signal when the check data is not checked; and when the flag control circuit outputs the flag signal, outputs the control signal to cause the selector to select the check data; A first-in first-out memory comprising: a control circuit for instructing the memory to write data output from a generator and read data output from the generator.