JPS59188756A - Scan bus controlling device - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware of a scan bus controlling device and the overhead of time by setting the word constitution of a scan data buffer means so that one parity bit is added to plural data bits. CONSTITUTION:A logical device 1 contains a scan bus 11. A scan bus controlling device 2 consists of a scan data buffer means 21 which is constituted by adding eight data bits and one parity bit, address counter means 22, holding register means 23, temporarily holding register means 27, and scan controlling means. Access from a maintenance diagnostic device 3 to the scan data buffer 21 is performed in the unit of word. Therefore, the quantity of hardware and overhead of time of the scan bus controlling device 2 can be reduced at the same time.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a scan path control device used in a data processing device, and particularly relates to the configuration and control of a scan data buffer for holding scan data. be.

(Prior Art) In FIG. 1 showing the prior art, a scan path control device 2 is connected to a logic device 1 including a scan path 11 and a maintenance/diagnosis device 3 for processing scan data, and a data processing device consists of a part of. In the scan path control device 2 shown in FIG. 1, 21 to 29 are the following components. That is, 21 is a scan data buffer means for holding scan-in data and scan-out data, and it is constituted by a RAM consisting of a plurality of words, in which one parity bit is added to each data bit.

Reference numeral 22 denotes an address counter means for instructing the scan data buffer means 21 to specify a word address, and has an increment function. Reference numeral 23 denotes a holding register means consisting of m bits for temporarily holding data from the maintenance/diagnosis device 3 and transmitting it to the scan data buffer means 21 one bit at a time. Reference numeral 24 denotes selection means for selecting scan-out data from the logic device 1 or the contents of a certain 1z-1Fi holding register means. 25 is a parity generation means for generating parity for the output data from the selection means 24. 26 is a parity check means for performing a parity check on the data read from the scan data buffer means 21. 2
Reference numeral 7 denotes temporary holding register means, which is provided to transfer data read bit by bit from the scan data buffer 21 to the maintenance/diagnosis device 3, and temporarily holds data consisting of m bits. 28 is a parity generating means for generating parity in the output data from the temporary holding register means 2T. 29 is a scan path control means for controlling scan-in operation and scan-out operation.

In the scanout control device 2 shown in FIG. 1, the scanout operation is performed as follows. That is, when the address counter means 22 is initialized, the contents of the shift path 11 are shifted by one bit each time a clock is supplied, and the data is sequentially output to the beginning of the scan path. This is added to the selection means 24, parity is generated via the selection means 24, and data with this parity added is written into the scan data buffer means 21. At this time, the address counter means 22 is incremented every time one bit is written.

When all the data in the scan path 11 has been shifted out as described above, the address counter means 22 is initialized again and the contents of the scan data buffer means 21 are read out to the temporary holding register means 27 one bit at a time. Once the predetermined m bits have been stored in the temporary holding register 21, this data is sent to the maintenance diagnosis device 3 as one word. Scan data buffer means 2
Parity is checked when data is read from the temporary holding register 2T, and parity is added when data is sent from the temporary holding register 2T.

Next, the scan-in operation is performed as follows. After the address counter means 22 is initialized, data to be scanned in from the maintenance/diagnosis device 3 is prepared in the holding register means 23 in units of one word each consisting of m bits. The contents of the holding register means 23 are sequentially sent out to the scan data buffer means 21 along with the parity via the selection means 24 in m times of 1 bit each, and sent to the scan data buffer means 21 designated by the address counter means 22. It is written to the address within 21. In this way, the scan-in data is stored in the scan data buffer means 21 in a plurality of times in units of one word. When the storage of scan-in data is completed for all of the scan data buffer means 21, the address counter means 22 is reset, and the contents of the scan data buffer means 21 are read out bit by bit and sent to the input end of the scan path 11. be done. Scan path 11
The scan-in data is 1 every time a clock is supplied to
Shifted bit by bit.

As explained above, in the conventional method, the word structure of the scan data buffer means 21 is one in which one parity bit is added to one data bit. /Data bus um for reading data bits (for example, 8 data bits) has a structure of 1 parity bit. Therefore, the capacity of the scan data buffer means 21 needs to be twice as large as the actual scan data, resulting in an increase in the amount of metal objects. In addition, the scan data buffer means 21
Since word conversion is required for writing/reading data to/from, there is also the drawback that there is a large time overhead.

(Object of the Invention) An object of the present invention is to set the word structure of the scan data buffer means so as to add one parity bit to a plurality of data bits, thereby facilitating writing/reading from an external device. It is an object of the present invention to provide a scan path control device that solves the above-mentioned drawbacks and achieves a reduction in the amount of metal objects and time overhead.

(Structure of the Invention) A scan path control device according to the present invention has a plurality of flip-flops connected in series in each device or package, and each time a clock is supplied, all data stored in the flip-flops is sequentially transmitted in the order of connection. It is therefore used in data processing devices with shifted scan paths.

A scan path control device according to the present invention includes scan data buffer means, address counter means, holding register means, and temporary holding register means.

The scan data buffer means is a buffer for storing the scan-out data output from the scan path and the scan-in data input to the scan path, and is composed of n words each consisting of m bits (m: positive integer). (
n: positive integer).

The address counter means is incremented each time the scan data buffer means is written and read, and is used to designate a word address of the scan data buffer means.

The holding register means is connected to the output end of the scan path and is for holding at least m bits of data bits scanned out, and when the held data reaches m bits, the holding register means This data is present in the data buffer means and is used to write this data to an address specified by the address counter means.

The temporary holding register means is connected to the output end of the scan data buffer means and is for temporarily holding scan-in data to be sent to the scan path, and is present in the scan data buffer means, The data word stored in the address counter means is read out in units of m bits from the data word specified by the address counter means, and the contents are sent bit by bit to the input end of the scan path. Data can be written from an external device to any word address in the buffer means, and data can also be read from one external device.

(Example) Next, a scan path control device according to the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of a data processing device including a scan path control device according to the present invention. In FIG. 2, numeral 1 is a logic device, which includes a scan path 11. In FIG. 2 is a scan path control device according to the present invention; 3
is a scan data buffer means for holding scan data and scan out data, for example,
It can hold a plurality of words each consisting of 8 data bits and 1 parity bit. The scan data buffer means 21 can be constructed from a conventional RAM. Note that the parity bit is added to increase the reliability of data. 22 is an address counter means for instructing the word address for the scan data buffer means ÷ 21, and has a function of incrementing each time the scan data buffer means 21 writes or reads. 23 is a holding register means for temporarily holding data written to the scan data buffer means 21; It has a function of holding l words while shifting the scan-out data bit by bit in the shift-out order. The holding register means 23 is a type of register capable of parallel input/output and serial input. 25 is a parity generating means for generating parity for the output data from the holding register means 23.

Reference numeral 27 denotes a temporary holding register means for holding one word of data read from the scan data buffer means 21, and has a function of sending data in units of words to the maintenance/diagnosis device 3, and a scan input function. This is a type of register that has the function of sending data to the scan path 11 bit by bit. Temporary holding register means 27
is a register capable of parallel input/output and serial output. It is a parity check means for parity checking the output data of the 26-digit temporary holding register means 27, and executes the check when data is read from the scan data buffer means 21. The second scan control means controls the scan-in operation and scan-out operation.

Next, the scan-out operation will be explained first. When the address counter means 22 is initialized, the shift lot 1
The contents of 1 are shifted by 1 bit each time a clock is supplied, and are serially input to the holding register means 23 from the beginning of the scan path 11. When the scan-out data up to 8 bits have been stored in the holding register means 23, parity is generated for the 8-bit data, and the data bits and parity bits are written into the scan data buffer means 21 at the same time. When writing is completed, the address counter means 22 increments and moves to the next word. in this way,
Data writing operation to the scan data buffer means 21 every 8 bits (1 word) and scan path 1
1, the contents of the scan data buffer means 21 are retrieved to the maintenance diagnostic device 3. Therefore, the address counter means 22
is initialized, the contents of the scan data buffer 21 are read out by one word to the temporary holding register means 27,
Next, it is sent to the maintenance diagnosis device 3. At this time, a parity check is performed by the parity check means 26, and the address counter means 22 is incremented. As explained above, data is sequentially read word by word.

Next, the scan-in operation will be explained. After initializing the address counter means 22, the data to be scanned in from the maintenance/diagnosis device 3 is set in the holding register means 23 in units of one word. The contents of the holding register means 23 are written to the address of the scan data buffer means 21 indicated by the address counter means 22, and the address counter means 22 is incremented. Once all the scan-in data is set in this way, a shift-in operation for the scan path 11 is then executed. Thereafter, the address counter means 22 is again initialized, the contents of the scan data buffer means 21 are read word by word into the temporary holding register means 27, the parity check means performs a parity check, and the address counter means 220 increments. It will be done. The data I''i read out to the holding register means 23 is sequentially sent one bit at a time to the input end of the scan path 11 as shift-in data.Every time a clock is supplied to the scan path 11, the shift-in data is shifted one bit at a time. ,
New shift-in data is read out from the scan data buffer means 21 to the holding register means 23 every time eight bits are shifted.

(Effects of the Invention) As explained above, the present invention achieves a reduction in the amount of hardware and time overhead at the same time by configuring the scan data buffer to be accessed in word units. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an example of a data processing device including a scan path control device according to the prior art. FIG. 2 is a block diagram showing the configuration of an embodiment of a data processing device including a scan path control device according to the present invention. 1...Logic device 2...Middle scan canvas control device 3...Maintenance/diagnosis device 11--Scan path 21--Scan data buffer means 22--Address quanta means 23...Holding register means 24-- ... Selection means 25 ... Parity generation means 26. 28 ... Parity check means 27 ... Temporary holding register means 29 -9 scan path control means Patent applicant NEC Corporation Agent Patent attorney Inoro Juju

Claims (1)

[Claims] A plurality of flip-flops are connected in series in each device or package, and each time a clock is supplied, the entire data stored in the flip-flops is shifted in accordance with the connection order. A scan path control device comprising: scan data buffer means comprising n words comprising m bits for storing scan out data output from the scan path and scan in data input to the scan path; address counter means for specifying a word address of the scan data buffer means, incremented each time the scan data buffer means is written and read; for holding at least m data bits,
When the retained data reaches m bits,
holding register means existing in the scan data buffer means for writing the data to an address specified by the address counter means; and a holding register means connected to an output end of the scan data buffer means and sent to the scan canvas. It is for temporarily holding scan-in data to be sent out, is connected to the scan delta balance means, reads out the data word specified by the address counter means in units of m bits, This is to send the contents bit by bit to the input end of the scan path, and it is possible to write data from an external device to any word address of the scan data buffer means, and also to send data to the input terminal of the scan path bit by bit. What is claimed is: 1. A scan path control device comprising: temporary holding register means from which data can be read.