JPH02136951A - Dma transfer system - Google Patents

Abstract

PURPOSE:To perform the DMA (direct memory access) transfer without carrying out any special process at the side of a microprocessor or an I/O controller even with the multi-bit bus width by performing the DMA transfer by an amount equal to the necessary number of transfer bytes with use of the valid byte status signal corresponding to the data transfer request signal received from the I/O controller. CONSTITUTION:The DMA transfer is carried out by an amount equal to the necessary number of transfer bytes with use of the valid byte status signal 4 corresponding to the data transfer request signal DREQ of a single time received from an I/O controller 2. In other words, the signal 4 showing the valid byte position to a single data transfer request is supplied to a DMA controller 1 from the controller 2 together with the signal DREQ. Thus the DMA transfer is carried out without performing any special process at the side of a microprocessor or the controller 2 even in the case plural bytes discordant to the data bus width are transferred.

Description

[Detailed Description of the Invention] [Summary] Regarding the DMA transfer method, when transferring multiple bytes that do not match the data bus width, there is no need for special processing on the microprocessor side or I/O control device. , a DMA controller, an I/O control device having the same bus width as the data bus width of the DMA controller, and storing data to be transferred to the I/O control device. or a storage device for storing transfer data from the I/O control device, the valid byte status corresponding to one data transfer request signal from the I/O control device; Depending on the signal, only the required number of transfer bytes are configured to be transferred by DMA.

[Industrial application field]

The present invention is directed to DMA (Direct Memory).
(Access) transfer method.

In recent years, the data processing speed of microprocessors and the processing speed of I/O control devices have improved. One of the reasons for this is that the bit width that microprocessors can handle is increasing, such as 16/32 bits.

Along with this, system data bus widths are also being standardized. In such an environment, the DMA controller interposes between the memory and the 1/O control device and transfers data, but the I/O control device does not necessarily request transfer in bytes that match the data bus width. There is. For this reason, the DM can perform byte-by-byte transfer even when the bus width is multi-bit.
A transfer method is desired.

[Conventional technology]

In the conventional DMA transfer using a multi-bit bus width, the DMA
The number of data transfer bytes to the controller is only allowed to be specified in units of data bus width. However, the I/O control device may issue a data transfer request in units of bytes other than units of data bus width. In such a case, a value greater than the number of data transfers requested by the I/O control device must be set in the DMA controller 17 to perform extra data transfers. This extra data is stored on the microprocessor side or! 70 and the data required by the control device. As another method, it is known that the data transfer is performed in several steps by re-configuring the operation settings of the DMA controller. However, in the former case, there is a risk that the data in the memory may be destroyed or that the I/O control device is forced to perform complicated control, and in the latter case, there is a risk that system performance may deteriorate.

FIG. 4 is a diagram for explaining an example of a conventional DMA transfer method, in which FIG. 4(a) shows a timing chart and FIG. 4(b) shows a memory state diagram. Here, it is assumed that the data bus width is 4 bytes, and that the storage device is composed of four memory sections that can be written in 1-byte units.

As shown in FIG. 4(a), for example, a 9-byte transfer request signal DREQ is output from the I/O control device,
When writing 9 bytes of data to the storage device, D M
Since the A controller can only set DMA transfer in units of 4-byte data bus width, the D
The MA controller settings are 12 bytes (4 bytes x 3
Zhou p, 11),! :Become. That is, the DMA controller receives the transfer request signal DREQ and outputs the transfer response signal *DACK for three pass cycles.

As shown in FIG. 4(b), in the first and second bus cycles, 4 bytes of data are each transferred to the storage device, and data is transferred to the four memory sections via data lines 1 to 4. valid data is written. This means that 8 bytes of data have been transferred.

However, in the third bus cycle, data line 1
Only 1 byte of data transferred to one memory section through
e becomes undefined data. As a result, three unnecessary bytes of data are written into the storage device, and it is necessary to distinguish these data as unnecessary data on the microprocessor side or the I/O control device side.

[Problem to be solved by the invention]

As mentioned above, in the conventional DMA transfer method, it is possible to improve the transfer speed by increasing the number of bits on the system bus side, but it is difficult to process fractional bytes from the I/O control device. is on the microprocessor side or I/
In the O control device, it was necessary to perform some kind of processing.

In view of the above-mentioned problem with the conventional DMA transfer method, the present invention is directed to the problem that special processing is required on the microprocessor side or I/O control device when transferring multiple bytes that do not match the data bus width. The purpose is to make it possible to perform DMA transfer without having to do so.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of a DMA transfer method according to the present invention.

According to the invention, a DMA controller l and an I/O controller having the same bus width as the data bus width of the DMA controller l are provided.
A DMA transfer method comprising an O control device 2 and a storage device 3 storing transfer data from the I/O control device 2 or a storage device 3 storing transfer data from the I/O control device 2. The effective byte status signal 4 corresponding to one data transfer request signal DRIEQ from the I/O control device 2 allows only the required number of transfer bytes to be transferred to the DMA.
A DMA transfer method is provided.

[For production]

According to the DMA transfer method of the present invention having the above-described configuration, one data transfer request signal D from the I/O control device 2
By the valid byte status signal 4 corresponding to the RE port,
Only the required number of transfer bytes will be transferred by DMA. That is, along with the data transfer request DREQ, -
A valid byte status signal 4 indicating the valid byte position for each data transfer request is sent from the I/O control device 2 to the DMA.
The signal is supplied to the controller 1. This allows DM to be sent in real time regardless of the data bus width of the I/O control device 2.
The A controller 1 can be notified of the number of bytes requested for data transfer, and even if the 170 control device 2 issues a transfer request that does not match the data bus width, the DMA controller 1 will respond by performing a transfer cycle for only the requested number of bytes. D
MA transfer will be executed.

As a result, even when transferring multiple bytes that do not match the data bus width, the microprocessor side or
DMA without the need for special processing in the O controller.
transfer can be performed.

〔Example〕

An embodiment of the DMA transfer method according to the present invention will be described below with reference to the drawings.

FIG. 2 is a block circuit diagram showing an embodiment of the DMA transfer method of the present invention. In the second session, bite control a
DMA controller 1 with no function, I/O control device 2 that controls the hard disk; hard disk drive (HDD) 7. and.

A system configured with a storage device 3 is shown.

Here, the data bus width is 4 bytes, and the storage device 3 is composed of four memory sections 31 to 34 in which data can be written one byte at a time.

The valid byte status bit (valid byte status signal) 4 sent by the I/O control device 2 is transmitted through, for example, four valid byte status signal lines provided for each 1-byte memory section 31 to 34. are supplied to the DMA controller 1 and one input of the corresponding NAND gates 11 to 14, respectively. The other inputs of these NAND gates 11-14 receive the upper bits of the address signal from the DMA controller 1 to the decoders 11-1.
The signals (select signals) decoded by NAND gates 51 to 54 are respectively supplied, and the output signals of NAND gates 51 to 54 are supplied to chip select terminals (*C3) of memory sections 31 to 34 corresponding to data lines 61 to 64. There is.

By the way, the management of the storage device 3 on the system is performed by a program (OS: Operating System),
That is, it is generally performed by a microprocessor unit (MPU). Also, D shown in FIG.
The MA controller 1 and I/O control device 2 are also controlled by the MPU. Therefore, the DMA controller l
When accessing the storage device 3 at the start of transfer, the MPU determines which data line to access first.
It is necessary to inform the MA controller 1 and the I/O control device 2, but these are done by register settings, and the I/O will not be notified unless set again by the MPU.
The O controller 2 is configured to always generate a valid status bit from the next byte position after transfer.

When considering data transfer in such an environment, HD
When reading data from D7, only the program itself and various data of the application are transferred, but in that case, the number of transferred hides is read in units of sectors. Generally, the sectors are 256.512. /O24 etc. are multiples of 4 and are not fractional values for the system. However, data + ID information.

Data 11E CC (Error CCo11ectin)
This does not apply in situations where you want to read out data other than code and data. That is, the ID information and ECC may have an odd value such as 5 or 7.9 bytes.

For example, when reading data of 9 bytes of ECC and 1 sector = /O24 bytes, the first /O24 byte is 4
The I/O control device 2 arranges the serial data read from the HDD 7 into parallel 4-byte units and issues a transfer request to the DMA controller 1. At this time, all four valid status bits become active, and data is written into all of the memory sections 31-34. Regarding ECC, the first two words (8 bytes) are transferred in the same way, but in the next cycle, only the one byte corresponding to data line 61 becomes valid and is written into memory 31. When all the transfer data is written, every time the DMA transfer ends.

FIG. 3 is a diagram for explaining the DMA transfer method in FIG. 2, and FIG. 3(a) shows a timing chart,
FIG. 5B shows a memory state diagram.

As shown in FIG. 3(a), the I/O control device 2
At the same time as asserting the data transfer request signal DREQ,
- Assert valid byte status bit 4 indicating the valid byte position for the data transfer request. The DMA controller 1 sends a data transfer response signal *DACK memory read signal *MR in response to a data transfer request signal DREQ.
D and address signals are asserted. At this time, I/
The O controller 2 sends valid data only to the data lines for which valid byte status bit 4 is active. By executing the write operation only in the memory section of the data line for which the valid byte status point 4 is activated by the external circuit or the DMA controller 1, only the number of bytes requested by the I/O controller 2 can be written. Data transfer will be performed.

When the I/O control device 2 detects that the valid hide status bit 4 (the fourth status signal of four valid byte status signals) for the data lines 61 to 64 has become active, the DMA controller 1 detects that Sends the next address signal. Then, the number of bytes being transferred in the current bus cycle is counted based on the number of valid bits of the valid byte status bit 4 and used for controlling the DMA controller l.

Therefore, even if the total number of bytes to be transferred does not match the unit of the data bus width, it is possible to transfer only the number of bytes requested by the I/O control device.

In the embodiment described above, the valid byte status signal 4 sent by the r/O control device 2 is transmitted through four valid byte status signal lines provided for each one-byte memory section 31 to 34. The signal is supplied to one input of the DMA controller 1 and the corresponding N A N D gates 51 to 54 via the DMA controller 1 .

However, although processing is required to distinguish the valid byte status signal 4 from other signals, the valid byte status signal 4 can be sent via the data bus or address bus without providing a new valid byte status signal line. You can also.

〔Effect of the invention〕

As described above in detail, the DMA transfer method according to the present invention transfers only the number of transfer bytes required by the valid byte status signal corresponding to the data transfer request signal from the I/O control device every time the DMA transfer is performed. Even when transferring multiple bytes that do not match the data bus width, the DMA transfer can be performed without requiring any special processing on the microprocessor side or the I/O control device.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the principle of the DMA transfer method according to the present invention, Fig. 2 is a block circuit diagram showing an embodiment of the DMA transfer method according to the present invention, and Fig. 3 is a block diagram showing the principle of the DMA transfer method according to the present invention. 2 is a diagram for explaining the DMA transfer method, and FIG. 4 is a diagram for explaining an example of the conventional DMA transfer method. (Explanation of symbols) 1...DMA controller, 2...I/O control device, 3...Storage device, 4...Valid byte status signal, 7...Hard disk drive, 11-14...・Decoder, 31-34...Memory section, 51-54...NAND gate, 61-64...Data line, DREQ...Data transfer request signal, Main DACK...Data transfer response signal, * MRD...
Memory read signal, main Ml... memory write signal. No.

Claims (1)

[Claims] 1. A DMA controller (1), an I/O control device (2) having the same bus width as the data bus width of the DMA controller, and storing data to be transferred to the I/O control device. A DMA transfer method comprising: a storage device (3) for storing transfer data from the I/O control device;
Valid byte status signal (4) corresponding to DREQ)
A DMA transfer method characterized in that only the required number of transfer bytes are transferred by DMA. 2. The storage device (3) has a plurality of memory units (31 to 34) in units of bytes, and each memory unit receives the valid byte status signal (4) and the DMA controller (
A logic gate (51) supplied with a select signal from
54), and DMA transfer is performed only to the selected memory section. 3. Claims in which the valid byte status signal (4) is transmitted via a plurality of valid byte status signal lines corresponding to the plurality of byte-based memory units (31 to 34). DMA transfer method described in Section 2.