JPS5960623A - Buffer controller - Google Patents

Abstract

PURPOSE:To perform careful buffer control to use a buffer memory area at its maximum, by setting an empty flag and making the used condition of the buffer memory area detectable. CONSTITUTION:When a flip-flop 8 is set upon the write request of a CPU, a data controlling circuit 7 compares the contents of the 1st and 2nd pointer registers 2 and 3 with each other at a conveyor circuit 4. When they are equal to each other, the data controlling circuit 7 checks the set or reset condition of the empty flag flip-flop 8 and judges whether a buffer memory 6 is in the full condition or empty condition. On the other hand, a data request signal DREQ1 from the CPU is kept waiting in accordance with the condition of the buffer memory 6. Namely, the signal DREQ1 is kept waiting to an input-output when the buffer memory 6 is full in the case of writing, but the signal DREQ1 is kept waiting when the memory 6 is empty in the case of reading out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a buffer control device, and more particularly to a buffer control device suitable for improving data processing capacity in an information processing system.

[Background technology and problems of the invention]

In an information processing system, the buffer memory provided between the input/output control unit and the central processing unit is controlled by storing one block of data (for example, one block in the case of a disk device, etc.).
Conventionally, a method of pre-fetching (by sector) has been used.

However, since this method controls data in block units, there is a loss of time in the initial state, and when the buffer memory is full (1!'1111)
/EMPTY There were problems such as not being able to manage detailed information, which was an obstacle to improving system performance.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer control device that eliminates the drawbacks of the prior art described above, increases data processing ability, and makes it possible to improve system performance.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a buffer control device according to an embodiment of the present invention. In the figure, 1 is a length register that stores the number of data transfers. 2 is a pointer register of the whistle 1 that indicates the address of the buffer memory 6 in response to a data request from the central processing unit [1]. A second pointer register 3 indicates the address of the buffer memory 6 in response to a data request from an input/output device. Reference numeral 4 is a comparison circuit that compares the contents of pointer registers 2 and 3 of the first whistle 2.

5 is a selector for selecting the contents of either the first or second pointer registers 2 or 3; 6 is a buffer memory. 7 is a data control circuit including a priority circuit. 8 is empty 1MP indicating the status of buffer memory 6
TY) is a flag flip-flop. Next, the input/output signals of the data control circuit 70 will be explained. J)I(l!:
Ql is a data request signal from a medium heat processing device 6 (not shown). DREQ2 is a data request signal from the input/output device.

DRQAI is a signal that notifies the central processing unit that the data request signal DREQI has been accepted.

DRQA2 is a signal that notifies the input/output device that the data request signal i) REQ2 has been accepted.

DXFRl is a signal indicating that data is being transferred between the buffer memory 6 and the central processing unit.

DXFR2 is a signal indicating that data transfer is being performed between the buffer memory 6 and the input/output device. Further, l(, P T I C is a carry signal of the first pointer register 2. RP'l''2C is a carry signal of the second pointer register 3.

In the following description, signal names will be described using only symbols.

FIG. 2 is a system diagram for explaining the interface between the buffer control device shown in FIG. 1, the central device, and the input/output device.
10 indicates input/output devices, respectively.

The operation of the present invention configured as described above will be explained below.

First, the first and second pointer registers 2, 3, length register 1, and empty flag flip-flop 8 are initialized. That is, all +1011 is input to the first and second pointer registers 2 and 3,
Further, a predetermined number of transfer words is input to the length register 1. Here, the initial setting of the empty flag flipflop 8 is set to a set state when the CPU writes to the input/output device W110, and vice versa, to a reset state when read.

Next, when the flip-flop 8 is set, the data control circuit 7 outputs the I) XFRI signal to the CPU, and as a result, C
Output DILEQI from PtJ to data control circuit 7. Furthermore, when the flip-flop 8 is reset, the data control circuit 7 sends DXI! to the input/output device 110! "The R2 signal is output, and as a result, I) REQ2 is output from the input/output device to the data control circuit 7. This DJtl) Ql
When outputting the signal and DREQ2 signal, the data control circuit 7
Then, perform the following actions.

First, when the flip-flop 8 is set in response to a write request from the CPU, the data control circuit 7 compares the contents of the first and second pointer registers 2 and 3 using the conveyor circuit 4. If the comparison results are equal, the data control circuit 7 checks the set or reset state of the empty flag flipflop 80 and determines whether the buffer memory 6 is full or empty.

On the other hand, the request signal D RE from the central processing unit CPU
Q1 is made to wait depending on the state of the buffer memory 6. That is, the input/output device 110 is made to wait when the buffer memory 6 is full when writing, and is made to wait when the buffer memory 6 is empty when writing reverse K flj5.

In addition, in general, the request signal D I from the input/output device 1/10
Q2 comes at regular intervals, so it is necessary to detect whether the data transfer was successful. This method is performed by determining the state of the buffer memory 6. In other words, when writing 1 to the input/output device [\I, /6,
A transfer error occurs when the buffer memory 6 is empty, and conversely, a transfer error occurs when the buffer memory 6 is full during reading.

Now, the above detection method will be specifically described as follows. For details, refer to the flowcharts in FIGS. 3 and 4.

1) Request signal [) It I (Q 1 is made to wait) When the contents of the first and second pointer registers 2 and 3 match and the empty flag flip-flop 8 is set.

2) Conditions in which a transfer error occurs when the request signals Dll and EQ2 arrive: When the contents of the first and second pointer registers 2 and 3 match and the empty flag flip-flop 8 is reset.

Incidentally, the empty flag flip-flop 8 is reset to indicate that R and PTIC are output from the first pointer register 2 and RPT2C is output from the second pointer register 3.

Through the processing described above, the data processing capacity of the entire system is significantly improved by the action of the buffer memory 60, although there is a temporary drop in service due to making the central processing unit CPU wait for the input/output device 110. It is possible.

In other words, in computer systems using the microprogram method, having independent hardware for data processing has less impact on the software (and is effective in simplifying the microprogram). be.

On the other hand, data processing ability in reading and writing data from input/output devices is greatly improved, and in particular, it becomes possible to immediately process read data.

〔Effect of the invention〕

As described above, according to the present invention, the area of the buffer memory can be used to the maximum extent, and the buffer status can be detected regardless of the data direction by initial setting of the empty flag, so that the data processing capacity can be greatly improved. Therefore, it is possible to obtain a new buffer control device that enables fine-grained buffer control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a buffer control device according to an embodiment of the present invention. FIG. 2 is a system diagram for explaining the interface between the buffer control device, central processing unit, and input/output device shown in FIG. FIGS. 3 and 4 are flowcharts for explaining the operation of the configuration shown in FIG. 1... l/ngs register, 2... first pointer register, 3... g2 pointer register, 4...
Conveyor circuit, 6... Buffer memory, 8... Empty flag 1) Tube flop. 1111' 1st person Kiyoshi Inomata = 11

Claims (1)

[Claims] a buffer memory interposed between a central processing unit and an input/output device; a first pointer register for specifying an address of the buffer memory in response to a data request from the central processing unit; and a first pointer register in response to a data request from the input/output device; A second pointer register that specifies the address of the buffer memory, a flip-flop that is set or reset by carry of the first and second pointer registers, and the contents of the first and second pointer registers are compared. A buffer control device comprising: a comparison circuit; and a control circuit that specifies waiting for a data request based on outputs from the flip-flop and the comparison circuit.