JPS6013360A - Storage device - Google Patents

Abstract

PURPOSE:To speed up the reading-out from a replaced area when reading-out from a defective area is accessed by reading out information stored in a memory device when the defective area is accessed. CONSTITUTION:The memory 60 enabled to access bits every bit has bits equal to the number of sectors included in each track of a track part and consists of an IC memory element enabled to execute high speed accessing. Counters 54, 59 are cleared to ''0'' and each bit of the memory 60 is also cleared to ''0''. The contents of a sector address register 52 are added to the upper 6 bits of the counter 54 by an adder 57 and the output of the adder is applied to a write/read part 92. The write/read part 92 checks a sector address part appearing next to a sector mark part, and if a sector address coincident to the output of the adder 57 is detected, reads out the write completion flag part, data part and data check code part of the sector, and applies the read-out data to an error detection correcting circuit 61.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a storage device such as an optical disk storage device, and particularly to one that enables high-speed reading even when a defective area exists in an information recording area.

[Background of the invention]

In conventional low-temperature disk storage devices, when a defective area, for example, a defective area due to a defect in a storage medium, is read, a replacement area to compensate for the defective area is always read. This replacement area is typically located a distance, eg, more than one track, from the defective area, and it takes a long time for the read head to position itself in this replacement area. In particular, optical disk storage devices require an order of magnitude more time for positioning than do blank disk storage devices due to structural limitations.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to speed up reading from a replacement area in a storage device when there is reading from a defective area.

[Detailed description of the invention]

The present invention is characterized in that in a storage device having both an information recording area and a replacement area for a defective area existing in the information recording area, a copy of information recorded in the replacement area is read out from the replacement area. The information is stored in another storage device that has a faster reading speed than the other storage device, and when the defective area is accessed, the information stored in the storage device on the other side is read out.

[Embodiments of the invention]

An embodiment of the present invention will be described below. Figure 1 is a block diagram of a computer system to which a disk storage device is connected. In the figure, the disk storage device consists of a control device 1 and a drive device 2.

The drive device 2 has a mechanism for rotating a loaded disk 3 for optical recording or optical recording, and a portion for writing and reading information on the disk 3. The control device 1 controls the operation of the drive device 2 and the flow of data between the central processing device 100 and the drive device 2 according to instructions from the central processing device 100 . Systems such as those described above are well known in this field.

Figure 2 is a diagram showing the tracks of the disk used in this embodiment. The disk has a plurality of trunks as information recording sections, and these trunks are divided into a track section 4 used for recording normal data and a track section 5 for alternate use.

In this embodiment, there is one replacement track section 5.

Each trunk is divided into multiple small areas called sectors.

Figure 3 is a diagram showing the format of sectors in the track section 4 of Figure 2. In the figure, 6 indicates the sector mark section indicating the beginning of the sector, 7 indicates the sector address section for identifying the sector, and 8 indicates the completion of writing indicating whether information has already been written to the sector. A flag section 9 is a data section into which data given from the central processing unit is written; 10 detects an error in the data section 9;
A data check code section 11 used to correct it if it is correctable is a gap in which no information is recorded. Note that other information may be included, but since it is not directly related to the present invention, a description thereof will be omitted.

, 3.

Figure 4 is a diagram showing the format of sectors in the replacement track section 5 of Figure 2. In the figure, the same parts as in the fang 6 figure are given the same numbers. This sector is used to record data in place of a certain sector in the track section 4 that is defective. Hereinafter, this alternative sector will be referred to as a replacement sector. What is different from Figure 3 is that there is a bad sector address part 12 at the rear of the data check code part 10 for recording the sector address of the bad sector that is being replaced by the replacement sector, and a bad sector address part 12. A defective sector address check code section 13 is added, which is used to detect an error and correct it if it is correctable.

Sector address part 7 of the sector in Figure 3 and Figure 4
consists of a track number for identifying a track and a sector number for identifying a sector within each track.

Sector numbers are set in order from the sector at the beginning of the track, 4.

This is what I did. In this embodiment, the sector mark section 6 and the sector address section 7 are written during the manufacturing stage of the disk, and the description will be made assuming that no reading error occurs in these sections.

FIG. 5 is a block diagram showing details of the control device 1 and the drive device 2 according to the present invention.

When the central processing unit accesses a disk storage device, it first issues an addressing command to specify which sector to access, and then specifies whether to write or read. Give a write command or a read command. When a write command is given, write data is sent from the central processing unit to the control device 1. The addressing command indicates the sector address of the first sector to start accessing and the number of sectors to be accessed. This number may be singular or plural, but if there is more than one, it is assumed that they all exist within the same trunk and do not span multiple tracks. The sector designated by this address designation command is the sector in the track section 4 in Figure 2.

The command sent from the central processing unit is received by the control unit 51, and the control unit 51 controls the entire operation including the drive device 2 based on the command. In addition, in figure 5 of the spear,
All signal lines between the control unit 51 and the parts controlled by it are not shown.

When an address designation command is given to the control unit 51, the sector address and number of sectors contained therein are determined by the sector address register 52 and sector number register 52, respectively.
It is set to B. and sector address register 52
The track number in is given to the head drive unit 91 in the drive device 2. As a result, the head driving section 91 positions the head on the track of the disk indicated by the given track number. This truck is one of the trunk parts 4 in Figure 2.

When this positioning operation is completed, the control unit 51 notifies the central processing unit that execution of the addressing command has been completed. The central processing unit receives this notification and sends out a write command or a read command. The case where a write command is sent will be explained below. The memory 55 is a memory in which each word is 1 byte, and is composed of an IC memory element or the like capable of high-speed access operation. The number of sectors included in each track of the trunk section 4 in Figure 2 is 64. The number of bytes of data recorded in the data section of each sector is 51.
2, the capacity of the memory 55 is 32,768 bytes. Counter 54 is a 15-bit counter. When a write command is given to the control unit, first the counter 54
is cleared. Then, the write data sent from the central processing unit is written one byte at a time to the address indicated by the counter 54 in the memory 55. counter 54
is counted and amplified by 1 every time writing is performed. When there is no write data from the central processing unit,
This is detected by the control unit 51, and the contents of the counter 54, which has already counted up due to the writing of the last data, are stored in the register, 7.

It is moved to the star 56. At this time, the counter 54 indicates a value equal to the number of bytes written to the memory 55.

Further, the number of bytes of write data sent from the central processing unit does not necessarily have to be an integral multiple of 512.

When the head positioning operation by the head drive unit 91 and the reception operation of the write data by the memory 55 are completed, the counter 54 is cleared to 0 and is controlled to indicate the start address of the memory 55.

After this, the contents of the sector address register 52 and the counter 5
The upper six pits of 4 are added by the adder 57, and the output thereof is given to the write/read section 92 in the drive device 2. The output of the adder 57 at this time indicates the start address of the sector in which data is to be written. Write/read section 9
No. 2 is adapted to read the sector address section of the sector when a sector mark section is detected, whether writing to the disk or reading from the disk. Write/read unit 92, adder 5
Sector address equal to the output of 7, 8.

If a write error is detected, first write a predetermined pattern to the write completion flag section of that sector, then write 512 bytes of data read from the memory 55 to that data section, and then generate a check code in the data check code section. Write the output from circuit 66. The check code generation circuit 66 is for generating an error check code for write data. 512 from memory 55
To read byte data, reading the address indicated by the counter 54 and the count amplifier of the counter 54 may be repeated until the lower 9 bits of the counter 54 become all "0" again.

Note that when the lower nine pits of the counter 54 become all "0", the upper six pits are incremented by one.

During the above operation, the contents of the counter 54 and the contents of the register 56 are compared by the comparison circuit 58. Before a match signal is output from the comparison circuit 58, the counter 5
When the lower 9 bits of 4 are all 10'', the contents of the sector address register 52 and the upper 6 bits of the counter 54 are added in the adder 57, and the memory is transferred to the next sector in the same way as before. New 512 read from 55
Bytes of data are recorded. Furthermore, if a match signal is output from the comparator circuit 58 before the lower 9 bits of the counter 54 become all "0", it means that the write data given from the central processing unit is exhausted before the recording of 512 bytes is completed. means. In this case, the fixed data from the register 50 is given to the write/read section 92 instead of the read data from the memory 55 until the lower 9 bits of the counter 54 become all "O".
2 records data of 512 hides. counter 54
If a match signal is output from the comparator circuit 5B at the time when the lower 9 bits of the register 5B become all "0", the register 5
Fixed data transmission from 0 does not occur.

The control unit 51 detects that the match signal from the comparison circuit 58 has already been output and that the contents of the sector number register 53 match the value indicated by the upper 6 bits of the counter 54. Terminate the write operation.

Immediately following the above write operation, a check operation is performed to verify whether the write operation was performed correctly. This operation is as follows. 59 is a 6-bit counter, and 60 is a memory that can be accessed in units of 1 bit. The memory 60 has a number of bits equal to the number of sectors (64) included in each track of the track section 4, and is capable of high-speed access. Consists of elements.

First, counters 54 and 59 are cleared to 0, and memory 6
Each bit of 0 is also cleared to 0. Similarly to the write operation, the contents of the sector address register 52 and the upper 6 bits of the counter 54 are added by the blade calculator 57.
The output is given to the write/read unit 92. The output of the adder 57 at this time indicates the start address of the sector into which data has been written by the write command. The write/read section 92 examines the sector address section that appears next to the sector mark section, and if a sector address matching the output of the adder 57 is detected, the write completion flag section and data of sector 11 are detected. The data check code section and the data check code section are read, and these are input to the error detection and correction circuit 61. The error detection and correction circuit 61 checks whether the write completion flag section is in a predetermined pattern or not, and also checks the data section based on the data check code section. If the write completion flag section does not have a predetermined pattern, or if the data section has an error that cannot be corrected, an error signal indicating that the sector is a defective sector is output. This error signal is written as "1" at the address indicated by the counter 59 of the memory 60. 0'' is written to the iai where no error signal is output. The counter 54 counts up at the same speed as during the write operation, and by the time the beginning of the sector mark of the next sector reaches the head position, The upper 6 bits are updated by 1. The counter 59 is incremented by 1 each time the memory 60 is written.

During the above operation, the contents of the counter 54 and the contents of the 12 register 56 are compared with 1i! 858 for comparison. If the lower 9 bits of the counter 54 become all "0" before a match signal is output from the comparison circuit 58, the contents of the sector address register 52 and the new contents of the upper 6 bits of the counter 54 are added to the adder. 57, and the new sector is checked to see if it is a bad sector in the same manner as before, and the result is written to the memory 6o.

The control unit 51 detects that the match signal from the comparison circuit 58 has already been output and that the contents of the sector number register 53 match the value indicated by the upper 6 bits of the counter 54, thereby Terminate the check operation. At the time this check operation is completed, the bit corresponding to the defective sector of the memory 6o is set to "1".

Following the above check operation, a write operation to the replacement sector is immediately performed to compensate for the defective sector.

This operation is as follows. The track number of the replacement track is recorded in the register 62. The contents of the register 62 are given to the rad moving section 91 in place of the track number from the sector address register 52. Thereby, the head driving section 91 positions the head on the track indicated by the given trunk number. The replacement sectors on the replacement track are used in the order in which they are arranged on the track, and register 6
8 is set to the start address of the replacement sectors that have not yet been used. 63 is a 6-bit counter.

When the head positioning operation by the head drive unit 91 is completed, the counter 59 is first cleared to 0, and the register 6
The contents of 8 are transferred to counter 63 via register 64. The contents of the counter 65 are given to the write/read controller 92 in place of the output of the adder 57. When the write/read unit 92 detects a sector address equal to the contents of the counter 63, it writes the required pattern into the write completion flag section of the replacement sector, and writes the data section, data check code section, and defective sector address section. and write the data obtained as follows into the defective sector address check code section.

When the address indicated by the counter 59 of the memory 60 is read and the read data is 0'', the counter 59
Only one is counted up.

When the read data of the memory 60 is 1'', the counter 59 does not count up and the update of the counter 59 is temporarily stopped. Note that the read operation of the memory 60 and the count amplification operation of the counter 59 are performed at high speed. The time it takes for the counter 59 to stop updating is very short compared to the rotational speed of the disk.The data read from the memory 60 is ?+1''
In this case, the contents of counter 59 are transferred to the upper six bits of counter 54. Then, the counter 5 of the memory 55
4 is indicated and the count up of the counter 54 is repeated until the lower 9 bits of the counter 54 become all "0" again, 512 bytes of data is read from the memory 55, and it is checked. The code is applied to the write/read unit 92 through the code generation circuit 15 and 66.

After that, the contents of the sector address register 52 and the contents of the counter 59 are added by an adder 65, and the output is passed through the check code generation circuit 66 to the write/read unit 92.
given to. In this way, the write/read unit 92 obtains the 5
The 12-byte data and its error check code are recorded in the data section and the data check code section, respectively, and the defective sector address and its error check code obtained based on the output from the adder 65 are recorded in the defective sector address section and the defective sector address section, respectively. Record in the sector address check code section. When recording to one alternate sector is completed, counters 59 and 63 are incremented by one. As a result, the updating of the counter 59 is stopped again when the read data of the memory 6o becomes "1", and the allocation to the next alternate sector is performed in the same manner as before.

During the above operation, the contents of the counter 54 and the contents of the register 56 are compared by the comparison circuit 58, and the result is 16.

Therefore, if a match signal is output from the comparison circuit 58 before the lower 9 bits of the counter 54 become all "0", the lower 9 bits of the counter 54 become all "0".
Fixed data from the register 50 is given to the write/read section 92 in place of the read data from the memory 55. The circumstances at this time are the same as when a write operation is performed.

The control unit 51 detects that the match signal from the comparison circuit 58 has already been output and that the contents of the sector number register 53 match the value indicated by the upper 6 bits of the counter 54, thereby Terminates the write operation to the alternate sector.

In this state, the register 64 holds the first address of the alternate sector to which writing was performed this time, and the register 68
holds the first address of a replacement sector that has not yet been used.

Immediately following the write operation to the alternate sector described above, an alternate sector check operation is performed to verify whether this operation has been performed correctly. This operation is as follows. First, the contents of the register 64 are transferred to the counter 63 and provided to the write/read section 92. When the write/read unit 92 detects a sector address equal to the contents of the counter 65, it reads the write completion flag part, data part, data check code part, bad sector address part, and bad sector address check code part of the replacement sector, These are input to the error detection and correction circuit 61. The error detection and correction circuit 61 checks whether the write completion flag is in a predetermined pattern, checks the data part based on the data check code part, and further checks the bad sector address part based on the bad sector address check code part. To check. If the write completion flag part does not follow the specified pattern, or if the data part has generated an uncorrectable error, or if the bad sector address part has generated an uncorrectable error, An error signal indicating that the replacement sector is a bad sector is output.

When the reading of one alternate sector is completed, the counter 63 is incremented by one, provided that no error signal is output from the error detection and correction circuit 61, and the next alternate sector is read. However, if an error signal is output, the alternate sector write operation is performed again from the beginning. Even in this case, since the contents of the register 68 are transferred to the counter 63 via the register 64, there is no fear that data will be written again to the defective replacement sector. In this alternate sector check operation, the contents of the counter 66 and the contents of the register 68 are compared in the comparator circuit 69, and the error signal from the error detection and correction circuit 61 is not output even once. If a match signal is output, it means that writing to all alternate sectors has been performed correctly, and in this case, the control unit 51 ends the alternate sector check operation.

The above is the operation when the write command is executed. At the end of the alternate sector check operation, the control unit 51 notifies the central processing unit 19° of the completion. Then, the control unit itself performs the read operation of the alternate sector. This operation is as follows.

71 is a memory having 15-bit words equal to the number of replacement sectors included in replacement track 5 in Figure 2;
73 is a memory having blocks of 512 bytes in a number equal to the number of words of the memory 71, and 73 is a memory having a number of 1-bit words equal to the number of words of the memory 71, each of which is an IC memory element capable of high-speed access operation. Consists of etc. One word in memories 71 and 73 and one block in memory IJ72 are simultaneously designated by counter 67.

Now, before the alternate sector read operation is performed, counters 63 and 67 are cleared to 0. The contents of the counter 63 are then given to the write/read section 92 . In the write/read section 92, when a sector address equal to the contents of the counter 63 is detected, the write completion flag part, data part, data check code part,
The bad sector address part and the bad sector address check code part are read out. The defective sector address section and data section are then written through the error detection and correction circuit 61 to the locations indicated by the counters 67 of the memories 71 and 72, respectively.

On the other hand, the error detection and correction circuit 61 outputs an error signal if the replacement sector is a defective sector based on the same determination criteria as in the replacement sector check operation. This error signal is set to 1 at the address indicated by the counter 67 of the memory 73.
"0" is written if no error signal is output. When reading of one alternate sector is completed, the counter 6! I and 67 are counted up by one, the next alternate sector is read, and the same operation as before is performed. During the above operation, counter 6
A comparison circuit 69 compares the contents of 3 and the contents of register 6B. Until a match signal is output from the comparator circuit 69, the read operation of the alternate sector and the memory 71, 72 are performed.
．． The write operation to 73 is repeated. When a match signal is output from the comparison circuit 69, the control unit 51 ends the alternate sector read operation.

The above alternate sector read operation is performed every time execution of a write command is completed. Therefore, the memories 71 and 72 are in a state where the data part and sector address part of replacement sectors for all the defective sectors detected during the execution of the previous write commands are written, and the data part and sector address part of the replacement sector are written in the memories 71 and 72. Ready for command.

When a read command is given in this state, the operation is as follows. First, counters 54 and 59 are cleared, and each bit in memory 60 is also cleared. Next, the sector number register 53 starts with the sector corresponding to the sector address set in the sector address register 52.
Each sector is read by the write/read unit 92 by the number indicated by . Also, 1" is written to the pit corresponding to the bad sector of the memory 60. Up to this point, the process is the same as the check operation described above, but in addition, the 512-byte data read from the data section of each sector is Data is written to memory 55.

To write 512 bytes of data to the memory 55, it is sufficient to repeat writing the address indicated by the counter 54 and counting up the counter 54 until the lower 9 pins of the counter 54 are all added again. Therein, the control unit 51 terminates the read operation by detecting that the contents of the sector number register 53 and the value indicated by the upper six bits of the counter 54 match.

Immediately following this read operation, the next operation is performed. First, counters 54, 59, and 67 are cleared. Next, read the address indicated by the counter 59 of the memory 6o, and if the read data is 0'', the counter 5
A count-up operation of 9 is performed. When the read data from the memory 6o is 1'', the contents of the sector address register 52 and the contents of the counter 59 are added by an adder 65, and the output thereof is given to the comparison detection circuit 7o.

Further, the contents of the addresses indicated by the counters 67 of the memories 71 and 73 are read out to the comparison detection circuit 7o, 23.

It will be done. This comparison output circuit 70 detects that the output of the adder 65 and the read data from the memory 71 match and
It outputs a signal when the read data from the comparison detection circuit 70 is 0''. If no signal is output from the comparison detection circuit 70, the counter 67 is incremented by 1, and the memories 71 and 73 are read again. In the comparison detection circuit 7o, when the signal is output, the gate 74
is opened, the 512-byte block indicated by the current counter 67 in memory 72 is read out one byte at a time, and this data is written to memory 55. In this case, the contents of the counter 59 are moved to the upper six bits of the counter 54, and writing to the address indicated by the counter 54 in the memory 55 and counting up the counter 54 are performed by the counter 54.
The process is repeated until the lower 9 bits of 9 bits become all 60'' again.

When the lower 9 bits of the counter 54 become all "0",
Counters 59 and 67 are counted up by one.

As a result, the updating of the counter 59 is stopped again when the read data of the memory 60 becomes '1'', and the block of the memory 72 is written to the memory 55 in the same manner as before. When the contents of the counter 59 become 0 due to the update, all data from the data section of the bad sector in the memory 55 has been replaced with data from the memory 72, that is, correct data from the data section of the replacement sector. Therefore, the counter 54 is cleared, and the counter 54 in the memory 55 is
The reading of the address indicated by and the count amplifier of the counter 54 are repeated. The read data from memory 55 is sent to the central processing unit. During this operation, the control unit 51 compares the upper six bits of the counter 54 and the contents of the sector number register 53, and when the two match, the read operation of the memory 55 is terminated.

The above is the operation when the read command is executed, and when this operation is completed, the control unit 51 notifies the central processing unit that the execution of the read command has been completed.

According to the device as described above, all the data recorded in the data portion of the alternate sector is stored in the memory 72 that can be accessed at high speed, so even if it is necessary to read the alternate sector, even if it is necessary to read the alternate sector, This makes it possible to read out data quickly.

Therefore, data requested by the central processing unit can be transferred quickly, and performance as a disk storage device is improved.

Note that in the above embodiments, the alternate sector read operation is performed every time a write command is completed, but this is not necessarily the case. However, in this case, depending on when the read command is given, all the data recorded in the data section of the alternate sector may not be stored in the memory 72 and may be transferred to the memory 55. Even if data from a bad sector is mixed in the read data, it may not be possible to compensate for it. Therefore, in this case, based on the fact that there was no output from the comparison detection circuit 70 at that point, Alternate sector read operations may be performed. Also, alternate sector read operations may be performed when the power of the device is turned on or the disk is loaded. In other words, because the power was previously turned off, the memory 71° Even if the contents of memory 72, 73 have been erased, or even if the contents of memory 71, 72, 71 are no longer valid because another disk was previously loaded, when the power is turned on again or a new If an alternating sector read operation is performed when loading a disk, the contents of the memo I771.72.73 can be made valid.

Note that in the execution operation of the read command, a case has been described in which the drive device 2 first performs the read operation and then the memory 72 performs the read operation, but the sector number register 5
When the value set to 3 is 1, control may be performed as follows. First, the contents of the sector address register 52 are given as they are to the comparison detection circuit 70, and it is checked in the manner described above whether or not the data of the sector to be accessed is in the memory IJ 72. Then, the corresponding block is read from the memo IJ72 and the read data is sent to the central processing unit. Otherwise, the corresponding sector is read from the drive device 2 using the method already described, and the read data is sent to the central processing unit. In this way, if the data in the sector you are trying to access happens to be stored in the memory 72,
Since the data is directly read from the memory 72, the read speed is improved.

Furthermore, although the case has been described in which alternate sectors are set on one common track, they may be set on multiple tracks. For example, alternate seftara may be set at a specific position on the same track as the defective sector. In the alternate sector write operation in this case, the track number of the sector address register 52 may be directly supplied to the head drive section 91, and a specific value may be set in the register 68. Further, the replacement sector may be set both in a common track and in the same track as the defective sector. In any case, the used replacement sectors can be identified later by 28U, and when reading the replacement sectors, the track number and sector number of each replacement sector can be set in the register 62 and counter 63, respectively. .

Further, although the case where there is one replacement track has been described, a plurality of replacement tracks may be provided. In this case, if it is detected that the contents of the register 68 exceed the number of alternate sectors in one track during the alternate sector write operation, a different track number is set in the register 62, and the register 68 is cleared. good. In this case, the capacity of the memo I771.72.73 needs to be multiplied by the number of replacement tracks. Furthermore, in the case where the number of sectors indicated in the sector number register 53 is plural, it has been explained that the sector does not span a plurality of tracks. However, in the case of a format in which a plurality of tracks are physically continuous in a spiral shape and the head can automatically follow them, there is no need to limit the number of sectors. In this case, the capacity of the memory 55 can be increased to increase the data transfer capability with one write command or read command.

Furthermore, although the case of a fixed-length data recording format in which sectors are units has been described, the present invention can also be applied to a variable-length data recording format in which records including a count section, key section, etc. are units.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a storage device that speeds up reading from a replacement area when there is reading from a defective area.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a computer system connected to a disk storage device, Figure 2 is a diagram for explaining tracks on a disk, Figures 6 and 4 are diagrams showing the sector format, FIG. 5 is a block diagram showing details of a control device and a drive device based on the present invention. In the figure, 1...control device, 2...drive device, 3...disk, 100...central processing Device, 51...control unit, 52
...Sector address register, 53...Sector number register, 54, 59.63.67...Counter, 58.
69... Comparison circuit, 55, 60.71.72.73
...Memory, 61...Error detection and correction circuit, 66.
. . . Check code generation circuit, 70 . . . Comparison detection circuit, 91 . . . Head drive section, 92 .

Claims (1)

[Claims] 1. In a storage device having both an information recording area and a replacement area for a defective area existing in the information recording area,
A memory comprising: a storage device in which a copy of the information recorded in the replacement area is stored; and means for reading out the information stored in the storage device when the defective area is accessed. Device. 2. In the storage device according to claim 1, the information recording area and the alternating area are formed on a rotatable disk, and the alternating area is provided on a different track from the information recording area. A storage device characterized by: