JP2826389B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device used for trimming a reference voltage or the like.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional semiconductor memory device for trimming such a reference voltage. In the conventional example of FIG. 5, the input of the trimming code signal is a serial input, and four trimming 4-bit memories are built in.
This is a configuration example of a semiconductor memory device in which a trimming signal is a 4-bit parallel output, and a readout of a trimming code signal is performed by a serial output.

As shown in FIG. 5, this conventional example converts a serial trimming code signal 208 input from an input terminal 87 into a parallel signal corresponding to a circuit to be trimmed 68, A serial / parallel conversion circuit 44 for outputting, a latch circuit 45 for receiving a signal from the parallel bus 303, and a latch circuit 4
A select circuit 46 for selecting and outputting the output signal of No. 5;
Memory circuits 47 to 50 receiving selection output signals of selection circuit 46 and storing corresponding selection output signals, respectively.
And tristate buffers 51 to 6 which individually receive the output signals of these memory circuits 47 to 50, respectively.
6 and the output signals of these tri-state buffers are connected to a parallel bus 304, and the parallel bus 304 is used as an input to perform parallel-to-serial conversion.
And a parallel-to-serial conversion circuit 67 that outputs the same.

Next, the operation will be described. In FIG. 5, a serial trimming code signal 208 is input from an input terminal 87 to a serial / parallel conversion circuit 44, converted into a parallel signal, and output to a parallel bus 303. The parallel signal is latched by the latch circuit 45, and the parallel trimming code signal output from the latch circuit 45 is input to the select circuit 46, and the memory circuit to which the trimming code signal is to be written is 47, 48, 49 and 50 are selected and output to the selected memory circuit. For example, in the select circuit 46, the memory circuit 47
Is selected, the trimming code signal is input to the memory circuit 47 and written. Through such a selection operation, the trimming code signal output from each memory circuit is input to the trimming target circuit 68, and predetermined trimming is performed. For example, when the circuit to be trimmed 68 is a reference voltage trimming circuit, the reference voltage is trimmed.

Here, the output signal from each memory circuit is supplied to the corresponding tristate buffer 51,
52, 53 and 54 and 55, 56, 57 and 58
59, 60, 61 and 62; 63, 64, 65
And 66, and output to the parallel bus 304 at individual timings via control signals input from control terminals 88 to 103 corresponding to the respective tri-state buffers. In the circuit 67, the signal is converted into a serial trimming code signal 211 via a system clock signal 209 input from a terminal 104, and output via an output terminal 105. 6 (a), (b) and (c) show the system clock signal 209,
FIG. 10 is a timing chart showing a control signal 210 input from a terminal 91 and a serial trimming code signal 211 output from an output terminal 105 for the tristate buffer 54. As an example, trimming output from a memory circuit 47 is shown. Is output as a serial signal through the tri-state buffer 54 to the output terminal 1.
5 shows an example of the output.

In this manner, by extracting the trimming code signal from the output terminal 105 in accordance with the trimming code signal 208 input from the input terminal 87, a defect check for the memory circuit is performed by comparing and comparing the two. Is performed.

[0007]

In the above-described conventional semiconductor memory device, when performing a defect inspection of a memory circuit, all bits of data stored in each of the built-in memory circuits are converted into parallel data. It is necessary to perform serial conversion and read out. Therefore, when the number of built-in memory circuits increases and the number of bits to be subjected to a defect inspection increases, there is a disadvantage that an enormous inspection time is required for that.

[0008]

The semiconductor memory device of the present invention, in order to solve the problem] is input with trimming code signal, comprising a memory circuit for writing the code signal for the tri <br/> timing, the main <br/> memory by the code signal trimming to be read from the circuit, a semiconductor memory device which performs a predetermined trimming to the target trimming circuit, during testing of the memory circuit, the main the predetermined test code signal is written in response to input of the read test code signal from <br/> memory circuit, a combination bit of the read test code signal,
By identifying said a predetermined same combination bit combination bit testing code signal, the semiconductor memory device including a test circuit comprising a combination bit identification circuit determines the quality of the memory circuit, the reading
The outgoing test code signals are all
A code signal of "0" and a code signal of all "1"
The first staggered code of “0101... 01”
Signal and the second zigzag pattern of "1010... 10"
And a first test signal comprising a code signal of
The test circuit is configured such that all of the first test signals are "0".
Code signal and code signal of all "1"
And the first staggered code signal and the second staggered code signal.
The combination bit identification receiving each of the bird-like code signals
It comprises a circuit .

It is to be noted that the combination bit discriminating circuit comprises a combination of levels of respective memory cells constituting the memory circuit.
Correspond to the combination bits of the predetermined test code signal.
As means for judging whether or not the combination is a corresponding level combination , "1" or "0" is set in response to the input of the read test code signal set corresponding to the level combination of each memory cell. May be configured by a logic circuit that outputs the identification level signal of "".

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the present invention, in which the trimming code signal is a 4-bit signal as in the conventional example. As shown in FIG. 1, the semiconductor memory device of the present invention comprises a trimming code signal input terminal 71, a system clock input terminals 72 and 76, control terminals 72, 73, 74 and 75, an output terminal 77 and a parallel terminal. The serial / parallel conversion circuit 1, the latch circuit 2, the select circuit 3, the memory circuits 4, 5, 6, and 7, the test circuit 8, the test circuit 8, State buffers 9, 10, 11 and 12 and a parallel / serial conversion circuit 13 are provided.

As apparent from FIG. 1, the difference from the conventional example of the present invention is that the memory circuits 4, 5, 6 and 7 correspond to the test code signal input from the input terminal 71.
Is output to the newly provided test circuit 8, and the combination bits of the test code signal are identified in the test circuit 8, and the corresponding test result is obtained. Thus, the combination bit identification signal output from the test circuit 8 is output to the corresponding tri-tristate buffers 9, 1 for each memory circuit.
0, 11 and 12 are output to the parallel bus 302 . That is, in the present invention, a specific combination bit of the test code signal output from each memory circuit is identified in the test circuit 8 for testing the memory circuits 4 to 7 in which the trimming code signal is selected and stored. Only the specific combination bit identification signal output from the test circuit 8 is output to the memory circuits 4-7.
The feature is that a test for determining the quality of the test is performed.

In FIG. 1, a serial test code signal 201 input from an input terminal 71 is a serial test code signal.
The signal is converted into a parallel signal by the parallel conversion circuit 1 and output to the parallel bus 301, latched by the latch circuit 2, and input to and stored in the memory circuits 4, 5, 6, and 7 via the select circuit 3. The operation is the same as in the above-described conventional example.

On the other hand, a test code signal output from each of the memory circuits 4, 5, 6, and 7 is included in the test circuit 8 and is included in each of the memory circuits 4, 5, 6, and 7.
(A test circuit 8 in FIG. 1)
(Not shown), the combination bits are identified, and the identification level signals output from the respective combination bit identification circuits are input to the corresponding tristate buffers 9, 10, 11 and 12, respectively. ,
Control signals 203, 204, 205 and 206 input from respective control terminals 72, 73, 74 and 75
Via the parallel bus 3 at respective individual timings.
02 to the parallel / serial conversion circuit 13
, The serial test code signal 20 via the system clock signal 202 input from the terminal 76.
7 and output via an output terminal 77.

FIGS. 4A, 4B and 4C show a system clock signal 202 and a system clock signal 202, respectively.
FIG. 4 is a timing chart showing a control signal 203 input from a terminal 72 and a serial trimming code signal 207 output from an output terminal 77 to the tristate buffer 9. As an example, a trimming code output from a memory circuit 4 is shown. The signal is transmitted to the tri-state buffer 9
, A serial signal is output from the output terminal 207 as a serial signal.

FIG . 2 shows a test circuit of a technique related to the present invention.
Is a view showing a road, a memory circuit 4 in FIG. 1, the selector circuit 3 associated therewith, in partial block diagram showing an excerpt only circuit components corresponding to each of the test circuit 8 and the tri-state buffer 9 is there. Therefore,
2, the serial / parallel conversion circuit 1, the latch circuit 2, and the tristate buffers 10 to 10 shown in FIG.
Circuit components corresponding to the serial / parallel conversion circuit 13 and the like are omitted, and only the portion corresponding to the memory circuit 4 is shown in the select circuit 3 and the test circuit 8 in FIG. Also, trimming times
Input line of the trimming code signal for road 14 also, only the line corresponding to the memory circuit 4 in FIG. 1 is described.

Referring to FIG . 2, a technique related to the present invention will be described.
The circuit of, in response to the trimming circuit 25, a select circuit 15 (the select circuit 3 in FIG. 1 shows only a portion corresponding to a memory circuit 4), the memory cell 17,
A memory circuit 16 (corresponding to the memory circuit 4 in FIG. 1) including the memory cells 18, 19, and 20, and a test circuit 21 including a combination bit identification circuit 22 formed by a NOR circuit 23 (memory of the test circuit 8 in FIG. (Only a part corresponding to the circuit 4 is shown) and a tristate buffer 24 corresponding to the test circuit 21. The output signal of the tri-state buffer 24 is
Although connected to one line of the parallel bus 303, the other lines are connected to the memory circuits 5 to 5 in FIG.
7 is a line included in the parallel bus 303 corresponding to
In FIG. 2, connection lines for these other lines are omitted because they are not necessary for explanation.

Now, a preset test code signal is set to “0000”, and when performing a defect inspection of the memory circuit 16, the memory cells 17 included in the memory circuit 16 are checked.
The operation in the case where it is determined that “.about.20” is “0” will be described. Combination bit identification circuit 22 in this case
Is formed by a NOR circuit 23, as shown in FIG. The test code signal output from the memory cells 17 to 20 is supplied to the test circuit 21 via terminals 78 to 81.
And included in the combination bit identification circuit 22
The signal is input to the R circuit 23. In this case, since the test code signals input to the NOR circuit 23 from each memory cell are “0”, the identification level signal output from the terminal 82 and input to the tristate buffer 24 is “1” level. Becomes This identification level signal is supplied to terminal 83
Is output to the parallel bus 303 at a predetermined timing via a control signal 208 input from the CPU. Similarly, although not shown in FIG. 2, test code signals output from other memory circuits are also input to the parallel bus 303, and these parallel test code signals are
Is converted into a serial test code signal and output.
In this case, if the serial test code signal output from the parallel-serial conversion circuit 67 is "1111", it is determined that all the memory cells in the built-in memory circuit are "0".

Next, an embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing a test circuit of this embodiment . Circuit components other than the test circuit are related to the present invention.
It is the same as in the case of related technologies

As shown in FIG. 3, a test circuit 26 in this embodiment includes a combination bit identification circuit 27 including a NOR circuit 31, a NAND circuit 32 and an inverter 3
A combinational bit identification circuit 28 including 3 and a NOR circuit 36
And a combination bit identification circuit 29 including inverters 34 and 35, a NOR circuit 39 and inverters 37 and 38
Combination identification circuit 30 including switches 40 to 4
3 is provided.

In FIG. 3, a test code signal "000" is provided in a test circuit 26 to terminals 82 to 85 corresponding to the test code signal from the memory circuit.
0, a combination bit identification circuit 28 corresponding to the test code signal “1111”, a combination bit identification circuit 29 corresponding to the test code signal “0101”, and a test code signal “1
There are provided four combination bit identification circuits including a combination bit identification circuit 30 corresponding to "010".

When checking the quality of a memory circuit, it is enormous to check all combinations of all bits, and it is meaningless. So, usually,
Whether all bits are "0" or "1", or "0101" or "1010" is a combination of whether or not each memory cell can be correctly written and read. Is enough. Therefore, to confirm that all the test code signals input to the test circuit 26 are “0”, the switch 40 is turned on, so that the test circuit 26 outputs a “1” level signal via the terminal 86. When the discrimination level signal is output and the test code signals are all “1”, the switch 41 is turned on, and the test circuit 26 similarly outputs the “1” level through the terminal 86. Is output. Also,
A test code signal of “0101” and “101”
By turning on the switches 42 and 43 for the "0" test code signal, the test circuit 26 outputs the "1" level discrimination signal in the same manner, that is, extremely simple. According to the method, it is possible to determine the quality of the memory cells in the memory circuit.

[0023]

As described above, the present invention provides a method for inspecting a memory circuit in a semiconductor memory device for defects.
By identifying the combination bits of the test code signal read from the memory circuit in response to the input of the test code signal, it is possible to shorten the time required for the defect inspection of the memory circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a partial block diagram of a technique related to the present invention.

FIG. 3 is a partial block diagram of an embodiment of the present invention.

FIG. 4 is a diagram showing a timing chart of signals in the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a diagram showing a timing chart of signals in a conventional example.

[Explanation of symbols]

1, 44 serial / parallel conversion circuit 2, 45 latch circuit 3, 15, 46 select circuit 4-7, 16, 47-50 memory circuit 8, 21, 26 test circuit 9-12, 24, 51-66 tristate buffer 13, 67 Parallel / serial conversion circuit 14, 25, 68 Trimmed circuit 17-20 Memory cell 22, 27-30 Combination bit identification circuit 23, 31, 36, 39 NOR circuit 32 NAND circuit 33-35, 37, 38 Inverter 40-43 switch

Continuation of the front page (56) References JP-A-1-286200 (JP, A) JP-A-64-39699 (JP, A) JP-A-63-140499 (JP, A) JP-A-63-37894 (JP) JP-A-63-191078 (JP, A) JP-A-2-283000 (JP, A) JP-A-1-98200 (JP, A) JP-A-57-189397 (JP, A) 57-179997 (JP, A) JP-A-57-27490 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 29/00

Claims (2)

(57) [Claims] An input of a trimming code signal is provided.
Comprising a memory circuit for writing the code signal for the trimming, by the code signal trimming to be read from said memory circuit, a semiconductor memory device which performs a predetermined trimming to the target trimming circuit, the test of the memory circuit sometimes, receives an input of the read test code signal from the memory circuit in which a predetermined test code signal is written, a combination bit of the read test code signal, combining bits of the predetermined test code signal In a semiconductor memory device provided with a test circuit including a combination bit identification circuit for judging pass / fail of the memory circuit by discriminating that the combination bit is the same as that of the memory circuit , the read test code signal is transmitted by the memory circuit.
All “0” code signals and all “1” code signals
.. and the first staggered "0101... 01"
The code signal and the second thousand of "1010... 10"
A first test signal consisting of a bird-like code signal;
Wherein the test circuit includes all of the first test signals.
"0" code signal and all "1" code signals
And the first staggered code signal and the first
The combination bits for receiving each of the two staggered code signals.
A semiconductor memory device comprising: an identification circuit . 2. The combination bit identification circuit determines whether a combination of levels of each memory cell forming the memory circuit is a combination of levels corresponding to a combination bit of the predetermined test code signal. In response to the input of the read test code signal set corresponding to the combination of the levels of the respective memory cells,
2. The semiconductor memory device according to claim 1, further comprising a logic circuit that outputs an identification level signal of "1" or "0".