JPH0316080U - - Google Patents
Info
- Publication number
- JPH0316080U JPH0316080U JP7648089U JP7648089U JPH0316080U JP H0316080 U JPH0316080 U JP H0316080U JP 7648089 U JP7648089 U JP 7648089U JP 7648089 U JP7648089 U JP 7648089U JP H0316080 U JPH0316080 U JP H0316080U
- Authority
- JP
- Japan
- Prior art keywords
- address
- bit
- accessed
- gate
- comparison
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図はこの考案の実施例の要部を示すブロツ
ク図、第２図はこの考案の他の実施例の要部を示
すブロツク図、第３図は半導体メモリ試験装置の
一般的構成を示すブロツク図、第４図は１アドレ
スが複数ビツトデータの被試験メモリを試験する
場合の従来構成の一部を示すブロツク図である。
Fig. 1 is a block diagram showing the main parts of an embodiment of this invention, Fig. 2 is a block diagram showing the main parts of another embodiment of this invention, and Fig. 3 shows the general configuration of a semiconductor memory testing device. FIG. 4 is a block diagram showing a part of a conventional configuration for testing a memory under test in which one address has multiple bits of data.
Claims (1)
し、そのアドレスにより被試験メモリをアクセス
し、その読み出された複数のビツトのデータを上
記期待値と論理比較部でビツトごとに比較を行う
半導体メモリ試験装置において、 上記論理比較部からのビツトごとの比較結果出
力の論理和をとるＯＲゲートと、 上記アドレスによりアクセスされ、上記ＯＲゲ
ートの出力が書き込まれる不良解析メモリと、 を含むことを特徴とする半導体メモリ試験装置
。[Claim for Utility Model Registration] An address and an expected value are generated from a pattern generation section, the memory under test is accessed using the address, and the data of a plurality of read bits is compared with the above expected value by a logic comparison section. In a semiconductor memory test device that performs a comparison for each bit, an OR gate that takes the logical sum of the bit-by-bit comparison result output from the logic comparison section, and a failure analysis memory that is accessed by the address and into which the output of the OR gate is written. A semiconductor memory testing device comprising: .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7648089U JPH0316080U (en) | 1989-06-28 | 1989-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7648089U JPH0316080U (en) | 1989-06-28 | 1989-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0316080U true JPH0316080U (en) | 1991-02-18 |
Family
ID=31617988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7648089U Pending JPH0316080U (en) | 1989-06-28 | 1989-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0316080U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01311500A (en) * | 1988-06-08 | 1989-12-15 | Hitachi Electron Eng Co Ltd | Fail bit analyzing system |
-
1989
- 1989-06-28 JP JP7648089U patent/JPH0316080U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01311500A (en) * | 1988-06-08 | 1989-12-15 | Hitachi Electron Eng Co Ltd | Fail bit analyzing system |
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