KR100262129B1 - Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits - Google Patents

Abstract

A memory integrated circuit chip of predetermined circuit topology has one phase logic driver on the chip.

The phase logic driver selectively converts the data written to and read from the addressed memory cells in the memory IC based on the locations of the addressed memory cells in the circuit phase of the memory array. The phase logic driver is preferably a logic circuit that embodies a Boolean function that defines the circuit phase. A method of inspecting and manufacturing such memory ICs is also described.

Description

A memory integrated circuit having a geometrically coupled logic driver on a chip and a method for inspecting and manufacturing the same.

1 shows a schematic topology circuit with a folded and twisted bit line structure.

2 is a block diagram of a memory integrated circuit including a memory array and a geometrically coupled logic driver constructed in accordance with the present invention.

FIG. 3 is a block diagram illustrating two memory array blocks in the FIG. 2 memory array.

4 is a block diagram of a preferred geometrical connection circuit of the FIG. 3 memory array block in accordance with one embodiment of the present invention illustrating a preferred twisted bit line structure.

FIG. 5 shows a table representing the geometrical connection circuit of the FIG. 4 array block.

FIG. 6 is a schematic representation of the global decryption circuit used in the geometrically coupled logic driver of FIG. 2 to represent certain areas in the memory array for data conversion.

FIG. 7 schematically illustrates a region decryption circuit used in the geometrically coupled logic driver of FIG. 2 to act on a selected region for data conversion.

FIG. 8 schematically illustrates the data conversion I / O circuit in the geometrically coupled logic driver of FIG.

9 is a flowchart illustrating a method for inspecting a memory integrated circuit having an on-chip geometrically coupled logic driver in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

30: memory IC 32: memory array

34: data I / O buffer 36: address decoder

38: read / write controller 40: address bus

42: I / O data bus

50: geometrically connected logic driver 52, 54: memory block

56: N sense amplifier 58: P sense amplifier

62: heat access line (line) 64: heat readout circuit

66, 68: odd row decryption circuit 70, 72: even row decryption circuit

74: row access line 76: joint

80, 82: secondary DC sense amplifier

100, 110: decryption circuit 104: AND gate

112, 114: XOR gate 120: I / O circuit

122: DC sense amplifier 124: XOR gate

126: data interleaver 128: record driver

The present invention relates to a memory integrated circuit having an embedded geometrical connection (node position) decryption circuit. The invention also relates to a method for inspecting and producing such circuits.

Memory integrated circuits (ICs) have one memory array with millions of memory cells used to store electrical charges representing binary data. For example, the presence of electrical charge in a memory cell is equal to the binary "1" value and the absence of electrical charge is equal to the binary "0" value. Memory cells are accessed via address signals in matrix lines. Once accessed, data is written or read from a memory cell addressed via a digit or bitline.

Memory cells, rows and column lines in a memory array are arranged in a specific arrangement or configuration, commonly known as a "geometric connection" (or "topology") circuit. Change.

One common design found in many memory geometric interconnection circuits is the "folded bit line" structure. In the folded bit line structure, the bit lines are arranged in pairs in which each pair is assigned a complementary binary signal. For example, one bit line in a pair is assigned one binary signal and the other bit line is assigned to process the binary signal DATA of the complement (the asterisk indicates binary complement).

The memory cells are connected to one of the bit lines of the folded pairs. During read and write operations, the bit lines are driven with opposite voltage magnitudes depending on the content of the data read from and written to the memory cells. For purposes of explanation, the following example illustrates a read operation of a memory cell that holds a charge representing binary method " 1. " The voltage potentials of two paired bit lines are equalized first with an intermediate voltage potential such as 2.5 volts. The addressed memory cell is then approached, and the charge in it is transferred to one of the bit lines, raising the bit line voltage slightly larger than the paired counterpart. A sense amplifier or similar circuitry senses the voltage difference across the pair of bit lines and increases this difference even further by increasing the voltage on the first bit line by 5 volts and reducing the voltage on the second bit line to zero volts. . The folded bit lines thereby output the output data in complementary form.

One type of folded bit line structure is a twisted bit line structure. FIG. 1 shows a twisted bitline structure with twisted bitline pairs DO / DO * -D3 / D3 * at junction 20 crossing the array. Memory cells are combined in bit line pairs throughout the array. Representative memory cells 22a-22n and 24a-24n are combined in bit line pair DO / DO *. Twisted bitline structures are deployed as a technique to reduce bit-line interference during chip operation.

Such noise becomes more and more problematic as memory size increases. Twisted bit line structures are therefore used in large memories such as 64Meg DRAM (dynamic random access memory).

Twisted bitline structures represent more complex geometric connections than simply folded bitline structures. Addressing memory cells in the FIG. 1 array are further included. For example, different addresses are used for memory cells on either side of the twist junction 20. As the memory capacity of memory ICs increases but the size is the same or shrinks, different noise problems and array constraints force the designer to think of more complex structures. As a result, the geometrical connections of these circuits become more complex and it becomes more difficult to explain mathematically because the complexity of each layer adds additional terms to the equations describing the geometrical connection. This can lead to more complex addressing techniques.

One problem that arises with memory ICs involves the inspection procedure. Examining memory ICs with complex geometric connections is increasingly difficult. To test ICs, a memory manufacturer uses a test machine preprogrammed by the manufacturer with a complex boolean function that describes the geometrical connection of the memory IC. This Boolean function is derived by the manufacturer. Conventional inspection machines can handle up to 6-bit addresses. However, as geometrical connections become more complex, 6-bit addresses may not fully address all individual cells for some test patterns. This makes the inspection device ineffective. Also, if the user wants to troubleshoot a particular memory device after some period of use, it is very difficult to derive the required Boolean function for input to the inspection machine without referring to the manufacturer.

The problem of inspection becomes even more apparent when one type of compression is used during inspection to accelerate the inspection period. It is common to write a check pattern of all "1" s and all "0" s into a group of memory cells. Consider the check patterns that write all " 1s " to the memory cells in the twisted bit line pair of FIG. Under check compression, one bit is used to address all four-bit line pairs DO / DO *, D1 / D1 *, D2 / D2 *, and D3 / D3 *. Under this conventional addressing technique, the task of placing "1" s in every memory cell needs to have a binary "1" or "0" through the bitline connected to that memory cell in order to accommodate "1"? This is not possible because cannot be distinguished from one single address bit. Thus, the inspection machine may not properly inspect memory ICs with complex geometrical connections. Conversely, checking memory ICs from cell to cell is undesirable because the test period is too long.

It is therefore an object of the present invention to provide a memory IC that facilitates such inspection and to provide a method for inspecting semiconductor memory ICs having complex geometrical connection circuits.

The present invention is consistent with the purpose of patent law to promote the development of science and useful technologies.

The present invention provides a semiconductor memory IC circuit having an on-chip geometric connection circuit. The memory IC includes a memory arrangement of a predetermined geometrical connection having a plurality of access lines connected to memory cells associated with the plurality of memory cells. Several access lines are arranged in pairs. One address decoder provides one address for selectively accessing one or more memory cells in the memory array and an I / O buffer temporarily holds data read from and written to the memory cell. The read / write regulator manages data writes and data reads that transfer data between the I / O buffer and addressed memory cells.

On-chip geometrically coupled logic drivers convert the data read and written from addressed memory cells. The geometrically coupled logic driver converts data for a given addressed memory cell based on the location of the addressed memory cell in the geometry of the memory array and does not convert data for another addressed memory cell. According to a preferred structure, the geometry logic driver includes a combination of logic gates that specify a Boolean function of the addressed selected bits, whereby the Boolean function defines the circuit function of the memory array.

2 shows a semiconductor memory IC chip 30 constructed in accordance with the present invention. The memory IC 30 includes a memory array 32 data I / O buffer 34, an address decoder 36 and a read / write regulator 38. Memory array 32 is composed of many memory cells arranged in predetermined geometrical connections. The memory cells are addressable via the column address signal CAO-CAJ and the row address signal RAO-RAK. The address decoder 36 receives the row address and column address from an external source (microprocessor or computer) and decrypts the addresses for internal use on the chip. Internal row and column addresses are performed via the address bus 40. The address decoder 36 thus provides one address (consisting of row and column addresses) for selectively accessing one or more memory cells in the memory array.

The data I / O buffer 34 temporarily holds the data read from and written to the memory cells in the memory array. Data I / O buffers, sometimes referred to as DQ buffers, are connected to memory array 32 via data bus 42 carrying data DO-DL. Read / write regulator 38 is connected to memory array 32 and data I / O buffer 34 to control timing and data write and read operations that transfer data between the I / O buffer and memory cells. Generate a control signal. In this way, the data I / O buffer and read / write regulator 38 forms the maturation I / O means for writing data to and reading data from the selected bit lines.

The memory IC 30 allows the geometrically connected logic driver 50 on the chip to be connected to the address bus 40 and the memory array 32. The geometrically coupled logic driver outputs one or more conversion signals through the I / O data bus 42 to selectively convert the data written to and read from the memory cells to account for the complexity in the IC circuit. Geometrically coupled logic drivers convert data for certain memory cells and not for other memory cells based on the location of memory cells in the circuit of the memory array.

In the present specification, the geometrically coupled logic driver 50 outputs the converted signal in the form of two sets of complementary signals ENINV / EVINV * and ODINV / ODINV *. Complementary EVINV / EVINV * signals are used to alternately or not convert even-bit data transmitted to the memory array via data bus 42. Similarly, complementary ODINV / ODINV * signals are used to alternately convert odd bits of data or not. These complementary signals are described in more detail below.

Geometrically coupled logic drivers 50 are uniquely designed for different memory IC outputs. Particular geometric connection designs of memory ICs are specifically described. Thus, the geometrically coupled logic driver 50 will be structurally different for various memory ICs. The logic driver is preferably implemented with a logic circuit representing a Boolean function that defines the geometrical connection of a given memory arrangement. By designing the geometrically coupled logic driver on a memory IC chip, there is no need to specifically program the test machine used to test the memory ICs with complex Boolean functions for all test batches of different memory ICs. The memory IC performs geometric connection adjustments without any external considerations by the manufacturer or user.

The present invention will now be described with reference to 64Meg DRAM. One preferred configuration of geometrically coupled logic driver 50 is described in detail below.

3 is a part of the memory array 32 of FIG. The memory portion has a first memory block 52 and a second memory block 54. Each memory block has a plurality of arranged memory cells connected in the intersection of row access lines and column access lines. The first memory block 52 is coupled between two sets of low voltage N and P sense amplifiers 56 and 60. The sense amplifiers are connected by a thermal access line 62, also commonly known as a bit or digit line. The column access line 62 is selected by a column decryption circuit 64 that decrypts the column address received from the address decoder 36 (FIG. 2).

Each memory block 52, 54 is connected to an odd row readout circuit 66, 68 and an even row readout circuit 70, 72, respectively. These decryption circuits select a row line 74 for access to the memory cells in the memory array block based on the row address received from the address decoder 36.

4 shows the memory array block 52 in detail. The memory array block has a plurality of memory cells (represented by small boxes) connected at the intersection of the row access line 74 and the column access line 62. The column access lines are arranged in pairs to form bitline pairs. Two sets of four bitline pairs are shown, each set comprising bitline pairs DO / DO *, D1 / D1 *, D2 / D2 * and D3 / D3 *. The upper or first set of bitline pairs is selected by column address bit CA2 = 0 and the lower or second set of bitline pairs is selected by column address bit CA2 = 1.

Even bitline pairs D0 / D0 * and D2 / D2 * are connected to the left or even primary sense amplifier 56. The odd bit line pairs D1 / D1 * and D3 / D3 * are coupled to the right or odd primary sense amplifiers 58. The even or odd sense amplifiers are alternately selected by the least significant bit of column address CA0, CA0 = 0 selects even primary sense amplifier 56 and CA0 = 1 selects odd primary sense amplifier 58. Four even bitline pairs D0 / D0 * and D2 / D2 * are further connected to two sets of I / 0 lines going to a secondary DC sense amplifier 80. Similarly, four odd bit line pairs D1 / D1 * and D3 / D3 * are connected to two different sets of I / 0 lines connected to a secondary DC sense amplifier 82. Secondary DC sense amplifiers 80 and 82 are coupled to a mating I / 0 buffer via the same data line (not shown in FIG. 4).

The DC sense amplifier 80 has the input conversion signals INV0 and INV1, and the DC sense amplifier 82 is coupled to receive the conversion signals INV2 and INV3. These signals are generated in geometrically coupled logic driver 50 (FIG. 2). These independent conversion signals convert data through bit lines D0 / D0 *, D1 / D1 *, D2 / D2 *, and D3 / D3 *. In another embodiment up to four separate converted signals may be used. In the illustrated geometrical connection described in detail below with respect to FIG. 5, the even data bits located on even bit lines D0 and D2 are the same throughout the array and the odd data bits located on odd bit lines D1 and D3 are the same. . Therefore, the two converted signal even conversion EVINV and the odd conversion 0DINV can be used in place of the four conversion signals INV0-INV3.

The individual bit line pairs have a twisted line structure and the bit lines in the bit line pair intersect the other bit lines in the memory array block center twisted 76 bit line pairs. The preferred structure uses a twisted configuration that includes overlapping bit lines from two bit line pairs.

Rowline 74 is used to access individual memory cells coupled to the selected row. Even rows 512 and 514... , 768, 770, etc., are coupled to an even row decoding circuit, and odd rows 513, 515,... , 769, 771, and the like are connected to the odd-numbered decryption circuit 66. Twisted junction 76 left memory cells are addressed via row address bit RA8 = 0 and twisted junction 76 right memory cells are addressed via row address bit RA8 = 1.

Some memory cells in an array block are excessive memory cells. For example, the memory cells combined in rows 512 and 768 are redundant memory cells. Such cells are used to replace defective memory cells that are detected during inspection. One preferred method for examining memory ICs with on-chip geometrically coupled logic drivers is described below. The method of replacing sufficient memory cells instead of defective memory cells is accomplished using conventional known techniques.

The IC arrangement of FIG. 4 allows the logic driver 50 to be driven for such a DRAM with a geometrical connection of 64Meg DRAM. The inventive derivation of a DRAM is described in detail below.

5 shows a table showing the geometrical connection of the arrangement block 52. This table contains example rows R512, R513, R514 to the left of torsion and example rows R768, R769, R770 and R771 to the right of torsion. The table is generated by examining the geometrical connection of the circuit in relation to the memory cell geometrical connection and assuming that the binary value "1" is written to all the memory cells in the array block 52.

Assume that memory cells are coupled to row R152. Such rows are addressed by RA8 = 0, RA1 = 0 and RA0 = 0. The upper bit line pairs are addressed via CA2 = 0. For bit line pairs D1 / D1 *, the memory cells through row R512 in array block 52 are combined into bitline D1. Thus, the table indicates that the bit line D1 should be written to replace the "1" data value in the memory cell. In the case of the bit line pair D0 / D0 *, the memory cells through the row R512 are combined into the bit line D0 *. Thus, the table is written so that the binary value "0" is written to the bit line D0 (that is, equivalent to writing the binary "1" to the complement bit line D0 *) to replace the data value of "1" in the memory cell. do. The table is completed in this way.

Note that some of the data bits that go into the table are binary "0" even if the check pattern is all "1". This result is due to the geometrical connection of a given circuit which requires inputting the complement of binary "0" or binary "1" in order to perform storage of binary "1" in the required cell.

For the geometrical connection of such a circuit, the even data bits located at even bit lines D0 and D2 are the same throughout the array. Similarly, odd data bits located on odd bit lines D1 and D3 are the same. Thus, two pairs of complementary signals can be used to selectively convert even and odd bit data for input into a memory cell. These complementary conversion signals are EVINV / EVINV * and 0DINV / 0DINV *, as shown in FIG. .

For the geometrical connection of FIG. 4 embodiment, the Boolean functions for the converted signals EVINV and 0DINV can be derived from the FIG. 5 table as follows:

6 and 7 show circuits implementing these Boolean functions for generating the converted signals EVINV and 0DINV based on the matrix address. These circuits are part of the geometrically coupled logic driver 50 for the 64 Meg DRAM embodiment described herein. The logic driver includes a full geometrically coupled decryption circuit 100 (FIG. 6) and a plurality of partially geometrically coupled decryption circuits 110 coupled to the decryption circuit.

The overall geometrical connection decoding circuit 100 of FIG. 6 is preferably located in the center of the memory arrangement. Represents an area of memory cells for possible data conversion based on the function of the row address signals RA0, RA0 *, RA1, RA1 *. The global geometrical connection decoding circuit 100 has two exclusive valid bits RA0, RA1 and one exclusive OR (XOR) gate 102 coupled to accommodate their complement. These row address bits are used to select specific row lines. The output of the XOR function is inverted into the overall even bit invert signal GEVINV. The combination of AND gates 104 combines the result of the XOR function with the column address bits RA8 and RA8 *. These row address bits are used to select a memory cell on either side of the torsion function 76. The result of this logic is the overall odd bit inversion signal GODINV.

Multiple partial geometric connection decoding circuits, such as circuit 110 in FIG. 7, are provided throughout the array to identify specific areas of the memory cell for possible data inversion. Each partial geometrical connection decoding circuit 110 consists of two XOR gates 112 and 114 which perform an XOR function of the overall inversion signals GEVINV and GODINV and the column address signals CA2 and CA2 *. The row address signals CA2 and CA2 * are selected to select a set of bit line pairs D0 / D0 * -D3 / D3 *. The partial geometric connection circuit 110 outputs the inverted signals EVINV and ODINV used in the partial array block.

8 shows even bit inversion I / 0 circuit 120 connecting internal even bit line pairs (ie, D0 / D0 * and D2 / D2 *) in the memory array with EVINV / EVINV *. Inverting I / 0 circuit 120 is shown coupled to bit line pairs D0 / D0 * for illustrative purposes. This inverts the data read from or written to the bit line pair D0 / D0 *. The structure of the odd bit inversion I / 0 circuit that couples the 0DINV / 0DINV * signals with the internal odd bit line pairs (ie, D1 / D1 * and D3 / D3 *) is the same and therefore only circuit 120 will be described in detail. will be. Inversion I / 0 circuit 120 is part of geometrically coupled logic driver 50.

The even bit inversion I / 0 circuit 120 has an XOR gate 124 that receives EVINV and EVINV * signals from the partially geometrically coupled decoding circuit 110.

The even bit inversion I / 0 circuit 120 has an XOR gate 124 that receives EVINV and EVINV * signals from the partially geometrically coupled decoding circuit 110. I / 0 circuit 120 also includes a crossover transistor arrangement or data inverter 126 and write driver 128. I / 0 circuit 120 is coupled to DC sense amplifier 122. Data is transferred to or from the bit line pair D0 / D0 * via data read lines DR / DR * and DC sense amplifier 122. DR / DR * under data reading is connected to data I / 0 buffer 34 (FIG. 2). The data is recorded or read out based on the data recording control signal DW input to the XOR gate 124. The output of the XOR gate 124 controls the write driver 128.

The EVINV / EVINV * signal is coupled to a crossover transistor array or data inverter 126. If the data will be inverted, the EVINV * signal is high and the EVINV signal is low. This causes the data inverter 126 to flip the data written to or read from the data line D0 / D0 *. Conversely, if the data is not inverted, the EVINV * signal is low and the EVINV signal is high. This allows the data inverter 126 to keep the data the same without inverting the data.

The geometrically coupled logic driver on the chip, which includes the overall geometrically connected circuit 100 (FIG. 6) and the partial geometrically connected circuit 110 (FIG. 7) and the inverted I / 0 circuit 120 (FIG. 8), Effectively invert data into certain memory cells as a function of column address. In the above embodiment, the logical driver is operated based on the functions of the row bits RA0, RA0 *, RA1, RA1 *, RA8, RA8 * and column bits CA2, CA2 *. By using the address bits, the logic driver can describe any geometrical connection circuit including a twisted bitline structure. In this way, the logic driver makes data inversion means for selectively inverting the data written to and read from the addressed memory cell based on the location of the addressed memory cell in the circuit connection of the memory array.

The above description is for a specific preferred embodiment of a 64Meg DRAM. However, the present invention can also be used for circuit connection and is not limited to the above structure. For example, the geometrical connection may use twisted rowline structures or complex memory block mirroring concepts or even more included twisted bitline architectures. Accordingly, another aspect of the present invention is directed to a method for generating a memory integrated circuit chip having a geometrically coupled logic driver on a chip. This method involves first designing an integrated circuit chip with a predetermined circuit connection. Next, a Boolean function representing the circuit connection of the integrated circuit is derived. Next, geometrically coupled logic circuits using Boolean functions are formed on the integrated circuit chip.

The memory IC of the present invention is preferable to the memory ICs of the prior art in that it has an on-chip geometric connection circuit. On-chip geometrically coupled logic drivers selectively invert the data written to and read from the addressed memory cells based on the location of the addressed memory cells in the circuit connections of the memory array. This use of predetermined geometric coupling circuits alleviates the need for manufacturer and user trouble shooters to preprogram the testing machine with boolean functions for specific memory ICs. Each memory IC instead has its own internal address resolver, which describes the circuit connections of any complexity. The inspection machine only needs to record the data inspection pattern into the memory arrangement without concern about whether the data should be reversed for geometric connection reasons.

Another benefit of the novel on-chip geometrically coupled decryption circuit is that it facilitates the inspection of the memory arrangement. On-chip geometric coupling circuits are particularly useful in check compression mode, in which many check bits are simultaneously written to and read from memory cells in the array. Thus another aspect of the present invention is directed to a method for inspecting a memory integrated circuit chip having a predetermined circuit connection and a geometrically coupled decryption circuit on the chip. This method will be described in connection with a particular embodiment of the 64Meg DRAM shown in FIGS. 4-8.

9 illustrates the inspection method of the present invention. The first step 200 is to access a group of memory cells in a memory array. One possible group of memory cells is the memory array block 52 in FIG. The selected number of test data bits is then written simultaneously to the group of memory cells accessed according to the test pattern (step 202). An embodiment check pattern includes all binary "1s" all binary "0s" alternating checker board patterns of "1" s and "0s" or other possible combinations of "1" s and "0s". do.

The on-chip geometrically coupled logic driver accommodates a large number of simultaneously written data bits. For example, 128x compression (ie, writing 128 bits simultaneously) or larger can be achieved using the circuit of the invention. Such test performance exceeds the capabilities of the test machine. Four secondary amplifiers are combined into one data line and the inspection machines can only record the same data with all four write drivers in the secondary amplifiers 80 and 82. However, the table in FIG. 5 shows that D0 and D2 must be in opposite states to D1 and D3 in order to actually write the same data into the memory cells. Therefore, the data on two of the four I / 0 lines must be reversed. There has never been a way to handle this condition. However, the on-chip geometric interconnection circuit of the present invention can handle this situation and can easily accommodate the maximum test address pressure to select all read / write drivers simultaneously. The next step 204 is to internally find certain memory cells in the accessed groups that must receive the inverted data to achieve the test pattern provided by the circuit arrangement of the memory array. In the embodiment table of FIG. 5, the data applied to the bit lines D0 and D2 on the upper axis in row R512 (CA2 = 0) should be inverted so that the check pattern of all "1s" can actually be written to the memory cell. The bits of inspection data written to the constant memory cells in step 206 are selectively inverted on the chip based on their position in the circuit connection. The remaining bits of the inspection data written to other memory cells (such as the upper bit lines D1 and D3 in row R512) are not inverted.

After the write and invert phase, the inspection data is read from the accessed groups of memory cells (step 208). The test data bits previously inverted and written into the constantly identified memory cells are selectively inverted again on the chip to return them to their desired state (step 210). In step 212, the bits of the test data read from the accessed groups of memory cells are compared with the bits of the test data written into the accessed groups of memory cells so that the memory integrated circuit has a defective memory cell. Determine if you have them.

The invention is not limited to the specific features shown and described, but modifications or variations are possible within the scope of the invention in accordance with the interpretation of the invention.

Claims (16)

Memory array 32 having a predetermined geometric connection circuit having a plurality of memory cells and a plurality of access lines coupled to associated memory cells, for selectively accessing one or more memory cells in the memory array 32 A decoder 36 for providing an address, an I / 0 buffer 34 for temporarily holding data written to and read from the memory cells in the memory array 32, the I / 0 buffer 34 Read / write adjuster 38 for managing data recording and data dominance, transferring data between the memory cells and the addressed memory cells, and selectively inverting the data written to and read from the addressed memory cells Selectively inverts the data for certain addressed memory cells in accordance with the location of the addressed memory cells in the geometric connection circuit of (32). Memory integrated circuit chip 30 including geometrically coupled logic driver 50 that does not invert data for other addressed memory cells. The method of claim 1 wherein the geometrically coupled logic driver 50 comprises a combination of logic gates that specify a Boolean function of selected bits in an address and that the Boolean function defines the geometrically coupled circuit of the memory array 32. Characterized by a memory integrated circuit chip (30) 2. A line according to claim 1, wherein the access lines comprise row lines and bit lines, the bit lines are arranged in pairs and the address decoder 36 selects a row address and bit line pair for selecting a row line. Characterized by providing an address comprising one column address for selection and the geometrically coupled logic driver 50 selectively inverting the magnetic field written to and read from the addressed memory cells as a function of the row address. Memory integrated circuit chip 30. 2. The apparatus according to claim 1, wherein the access lines comprise row lines and bit lines and the bit lines are arranged in pairs and as long as the address decoder 36 selects a row address and bit line pair for selecting a row line. Provide an address comprising a column address and the geometrically coupled logic driver 50 selectively inverts the data written to and read from the addressed memory cells as a function of both row address and column address. A memory integrated circuit chip 30. 2. The overall readout circuit (100) of claim 1, wherein the geometrically coupled logic driver (50) represents a region of memory cells in the memory array (32) for possible data inversion, and the memory array (32) for possible data inversion. Memory integrated circuit chip (30) comprising a plurality of partial readout circuits (110) representing specific regions of memory cells. The method according to claim 1, wherein the access lines comprise row lines and bit lines, the bit lines are arranged in pairs and as long as the address decoder 36 selects a row address and bit line pair for selecting a row line. A circuit providing an address comprising a column address and wherein the geometrically coupled logic driver 50 represents an area of memory cells in the memory array 32 for possible data inversion based on a function of a row address, A full decryption circuit 100 for outputting a full inverted signal and a plurality of partial decryptions representing a particular region of memory cells in the memory array 32 for possible data inversion based on the function of the full inverted signal and the column address. Memory integrated circuit chip (30) comprising a circuit (110). A plurality of memory cells and a plurality of row and column lines coupled to the associated memory cells, the bit lines arranged in pairs and a twisted line structure and the bit lines in the pair of bit lines twisted in the memory array 32. Provides a memory array 32 arranged to intersect other bit lines in a pair of bit lines, an address for selectively accessing one or more memory cells in the memory array 32, wherein the address selects a row line. An address decoder 36 comprising one row address and one column address for selecting one bitline pair, and an I / O for temporarily holding data read from and written to the memory cells in the memory array 32. A buffer for managing data writing and reading operations for transferring data between the zero buffer 34 and the I / 0 buffer 34 and the addressed memory cells A memory cell addressed in the memory array 32 with respect to the associated bitline pairs and torsion junction 76, selectively inverting data written to and read from the read / write regulator 38 and addressed memory cells Memory integrated circuit chip (30) comprising a geometrically coupled logic driver (50) that selectively inverts data for a given addressed memory cell based on its location and does not invert the data for other addressed memory cells. 8. The method of claim 7, wherein the geometric logic driver 50 comprises a combination of logic gates that specify a Boolean function of bits in a selected address, the Boolean function defining the geometric coupling circuit of the memory array 32. Memory integrated circuit chip (30) characterized in that. 8. The memory integrated circuit of claim 7, wherein the geometric logic driver 50 selectively inverts the data written to and read from the addressed memory cells as a function of both the row address and the column address. Chip 30. 8. The memory integration of claim 7, wherein the geometrically coupled logic driver 50 selectively inverts data written to or read from addressed memory cells as a function of both the row address and the column address. Circuit chip 30. 8. The memory according to claim 7, wherein the geometrically coupled logic driver is a full readout circuit (100) representing a region of memory cells in the memory array (32) for possible data inversion, and a memory in the memory array (32) for possible data inversion. A memory integrated circuit chip (30) comprising a plurality of partial readout circuits (110) representing cells specific regions. 8. The method of claim 7, wherein the geometrically coupled logic driver 50 represents an area of memory cells in the memory array 32 for outputting one possible inverted signal for possible data inversion based on the function of the row address. A total decryption circuit 100 and a plurality of partial decryption circuits 110 representing a particular region of memory cells in the memory array 32 for possible data conversion based on the function of the total inverted signal and the column address. Memory integrated circuit chip (30) characterized in that it comprises a. It has a predetermined geometric connection circuit, has a plurality of bit line pairs and a plurality of row lines arranged in a folded bit line structure, the bit line pair has a twisted bit line structure, the bit in the bit line pair Memory array 32 in which lines intersect other bit lines in bit line pairs at torsion junction 76 in memory array 32 and are coupled at the intersection of the bit line pairs and row lines of a plurality of memory cells. Address decoder 36, which provides addresses of a plurality of bits for selecting row lines and bit line pairs for selectively accessing memory cells in the memory area 32, selecting bit line pairs. Data I / 0 means 34 for reading and writing the hazard data, based on the location of the addressed memory cells in the geometric connection circuitry of the memory arrangement 32 And data inversion means for selectively inverting the data read from and written to the addressed memory cells, all memory concatenated with the same previous value data into selected bit line pairs in the memory array 32. Can be operated in one test mode for writing to cells, wherein the data inversion means are arranged into constant memory cells coupled to the selected bit line pairs based on the location of the addressed memory cells in the memory array 32. Selectively inverting the data input of the circuit and not inverting the data input to the other memory cells coupled to the selected bit line pairs. 15. The apparatus of claim 13, wherein the data contains alternating even and odd bits, the inverting means generating two sets of minor signals EVINV / EVINV * and 0DINV / 0DINV *, wherein the complementary EVINV / EVINV * signals are even. Used to selectively invert the data of bits and the complement 0DINV / 0DINV * signal is used to selectively invert the odd bit data, and the geometric connection circuitry of the memory array 32 is converted by the data inversion means. And the data of the odd bits inputted to the addressed memory cells coupled to the same rowline as the data of all the even bits inputted to the addressed memory cells coupled to the same rowline. Chip 30. An integrated circuit chip 30 having a predetermined geometric connection circuit is provided, wherein the integrated circuit chip 30 has a memory arrangement 32 having a plurality of memory cells and a plurality of access lines coupled to their associated memory cells. Derives a Boolean function representing the geometrical connection circuit of the integrated circuit 30, derives a Boolean function representing the geometrical connection circuit of the integrated circuit 30, and derives the integrated circuit chip Forming a geometrically coupled logic circuit on the chip (30) that implements the Boolean function. Access a group of memory cells in the memory array 32 according to an address to the memory cells, simultaneously write a selected number of test data bits into the memory cells of the group accessed according to the test pattern, and Internally locates certain memory cells in the accessed groups that should receive inverted data to achieve a check pattern for a given geometric interconnection circuitry, and writes them into certain memory cells according to the position of the cells in the geometric interconnection circuitry. Selectively inverts the test data bits on the chip, reads the test data from the memory cell groups without inverting the test data bits written to the other memory cells, and on-chip reads from the predetermined memory cells inverted previously. Selectively inverts the test data bits, and Comparing the test data bits written into the accessed groups with test data bits read from the accessed groups of memory cells to determine whether the memory integrated circuit 30 has defective memory cells Has a predetermined geometric connection circuit comprising a memory array 32 having a plurality of memory cells and a plurality of access lines coupled to the associated memory cells, the plurality of memory cells being excess with normal memory cells; A method for testing a memory integrated circuit chip (30) consisting of memory cells.