JPS6168800A - Memory test equipment - Google Patents

Abstract

PURPOSE:To decide a relief line to a defective bit in a short time by attaining read of plural bit constitution memory corresponding to mat unit in the unit of each bit in reading of a fail memory. CONSTITUTION:A fail data is read to a memory segmentation section 41 from an output terminal Do of a fail memory 34, a specific bit series in a word corresponding to the mat unit for analysis processing is selected and the result is outputted to a prescribed bus. A data processing section 43 of a defect analysis section 42 extracts the data of a prescribed bit on the bus to execute the count of a row line at each mat and the count of a column line for fail analysis processing. The relief line is decided at a CPU35 while taking the criteria into consideration. Thus, the analysis for defective bit relief discrimination is executed corresponding to the mat to reduce remarkably the analysis time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a testing device for semiconductor devices, and more particularly to a memory testing device that facilitates repair of defective bits in various semiconductor memories.

[Background of the invention]

2. Description of the Related Art Semiconductor devices, such as semiconductor memories, are tested by test equipment in order to test their quality. Generally, this type of test equipment has 256K DRAM, 64K
Targeted at devices such as S-RAMs that have a repair function for defective bits, the test results are completely stored in a fail memory to determine redundant lines, and are read out for fail analysis.

One of the conditions for this relief line analysis is that it is necessary to perform relief line determination according to the internal cell configuration (mat configuration) of the memory under test. The present invention relates to a memory test device for facilitating the relief line determination.

FIG. 1 describes a conventional semiconductor memory testing device of this type. As shown in FIG. 1, a pattern generator 1 outputs an address and a test pattern, and this signal is sent to a memory under test 2. After the pattern signal is temporarily stored in the memory under test 2, the comparator 3 compares the stored contents with the expected value output from the test pattern generator 1 while reading out the stored contents. The quality of the memory under test 2 is determined based on whether the
This is done by storing failure information corresponding to the output bit width of the memory at one address in the fail memory 4.

Conventionally, in this type of test equipment, when repairing and analyzing defective bits, "1" is extracted from each memory block of the fail memory 4.
” or “◯” defective information is read out in parallel and analyzed by the computer 5.

Alternatively, reading is performed with the same data width as when writing defective information, and row counting, column counting, etc. are performed for determining repair lines.

Therefore, when analyzing a specific bit sequence in each word of the memory under test, that is, when analyzing each mat correspondence of memory cells, a computer breaks down multiple bits bit by bit and assembles them into mat constituent units. There is a drawback that the larger the bit width, the more time it takes to analyze.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems in the prior art, and to provide a memory testing device suitable for determining repair lines for defective bits in a multi-bit memory in a short time.

[Summary of the invention]

The present invention is characterized by means for outputting test results in which one word of the memory under test has a plurality of bit configurations to read terminals of a plurality of fail memory blocks, and arbitrarily selecting data of a specific bit series within the word. , a means for reading in parallel corresponding to multiple bit configurations and a means for reading in multiple bit width units regardless of the bit configuration width of the memory under test are provided, and when reading from fail memory, it corresponds to mat units. The point is that it is possible to read out each bit of the multi-bit configuration memory.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 2 and 3. Second
The figure is an overall configuration diagram of the memory testing device, and FIG. 3 is a detailed circuit configuration diagram of the memory extraction section of FIG. 2. In FIG. 2, 21 is a pattern generator, 22 is a memory under test,
23 is a comparator for comparing and determining the output of the pattern generator 21 and the output of the memory under test 22; 34 is a fail memory;
35 is a computer, 36 is a data distributor, 37 is a multiplexer, 38 is an address shifter, 39
is a memory selector, 40 is an address distributor,
41 is a memory extraction section, 42 is a failure analysis section, 43 is a data processing section, 44 is an address generator, 45 is an instruction register,
46.47. ．． 48 indicates a switch.

In FIG. 1, an address is specified and a test pattern is written into the memory under test 22 shown in FIG. A comparison 2 judgment is performed using the write data as an expected value, and the result is written into the fail memory 34.

At this time, if the memory under test 22 is a memory with a multi-bit configuration, the output data of the comparator 33 is
Data distributor 36 distributes and stores the information in word units to each memory block within the memory block 4.

On the other hand, the write address of the fail memory 34 is switched to the address on the pattern generator 21 side by the multiplexer 37, and the input address is shifted by the address shifter 38 according to the number of words of the multi-bit memory.
A lower address AL and a fail memory address A to be given to the memory selector 39 are generated. By controlling the number of input addresses of the memory selector 39 that divides the memory blocks, this shifter can easily handle various multi-bit configuration memories. The address distributor 40 uses each selection signal selected by the memory selector 39 to match the number of words of the memory block and the memory under test. Further, the upper address AH from the address shifter 38 is input to the address input of the fail memory 34.
is directly applied, and the logic “1” or “0” of the failure signal preset to the data input terminal is sent to the fail memory 34.
Memorization of test results is performed by writing to .

The data distributor 36 and the address distributor 40 can be easily realized using a logical combinational circuit. Next, the operation of the fail data read system for determining the repair line of a defective bit will be explained.

Generally, in a multi-bit memory under test, the number of mat configurations, which is the number of memory cell blocks inside the memory element, is determined in proportion to the number of bits constituting one word, and the repair line for defective bits is determined for each mat. Several bottles are available within the cell. For example, in the case of a memory in which one word consists of 8 bits, there are 16 mats, and one relief line is prepared for each mat. Each of the 8 bits corresponds one-to-one to two mats. Therefore,
In failure analysis for determining a repair line, reading is performed in units of mats, that is, in units of bits within a word, thereby making later determination of repair lines easier.

Reading from the fail memory 34 is performed from the output terminal Do of the fail memory 34 to the memory cutout section 41 in FIG.
Here, a specific bit sequence within the word corresponding to the mat unit for analysis processing is selected and output onto a predetermined bus. The data processing section 43 of the failure analysis section 42 extracts data of predetermined bits on this bus, counts row lines and column lines for each mat, and performs fail analysis processing.

The determination of the relief line is finally determined by a computer based on the above-mentioned analysis data, taking into account determination conditions and the like.

The read address at the time of analysis is the address of the address generator 44 or the address from the computer, which is switched by the multiplexer 37 from the address at the time of testing and given to the fail memory 34. Further, various switching modes are set from the computer 35 side by rewriting the instruction register 45, and each unit is controlled. Control signal AL
L is used when the computer 35 directly accesses the fail memory 34 in units of data bus width by controlling the memory selection signal. The I10 mode control signal specifies the number of bits in the memory under test, and the I10 bit designation specifies arbitrary bits within one word.

Next, various read operations of the memory extraction section 41 will be explained based on FIG. 3.

In FIG. 3, 50 to 55 are output sofas, 56 is a decoder, 57 to 59 are output sofas, and 60 to 63 are gates.

First, the memory under test with a multi-bit configuration outputs 1 bit (1
In the case of 4110, the test result is stored in the memory block in the fail memory 34 in correspondence with the test address.

Memory blocks FDO to FD3 and FD4 to FD7 of the fail memory 34. FD8~FDII, FD12~FD
In the case of 8I10, the memory blocks FDO-FD7 and FD8-F of the fail memory 34 are stored sequentially in each memory block in 4-bit units in a sequence of 15.
The data is stored sequentially in the depth direction in units of 8 bits in a D15 sequence. To read these data, one is to read a specific bit series within one word, the other is to read in parallel in units of construction width, and further to read in units of all bits of the memory block according to each designation. .

First, for bit-by-bit reading within a word, the addresses within the mat to be analyzed are sequentially generated from the address generator 44. The multiplexer 49 switches the data FDO to FD15 one bit at a time each time the address changes.
I, . . . FD15 is read out and output from the output buffer 50 onto the DO bit on the data bus, and the multiplexer 51 specifies the 0 bit of the I10 bit so that D
o The test results of any of the FDO-FDs 15 output on the data bus are taken into the data processing section 43.

Next, in the case of 4I10, the output buffers 752 to 55 are selected via the decoder 56 and the gate 60.62 by the 2 bits of the memory selection address AL shifted by 2 bits by the address shifter, and the output buffers 752 to 55 are transferred to the data bus as 4 bits of data. FDo-FD3. on Do-D3. FD4～
FD7. FD8~FDII.

The test results of FD12 to FD15 are output in correspondence with each bit.

In the case of 8I10, the address shifter is shifted by 3 bits, and depending on 1 bit of the memory selection address AL, the output 0 signal of the decoder 56 operates the buffers 57 and 52, thereby changing the output data FDO of the fail memory 34.
The 8 bits of .about.FD7 are outputted to data buses DO.about.D7 corresponding to the bits. Similarly, when output 2 of decoder 56 occurs, buffers 58 and 54 are operated, and fail memory 3
8 bits of output data FD8-FD15 of No. 4 are output to data buses DO-D7. Multi-bit memory is
After reading according to the number of words, defective bits can be analyzed by the computer 35, but when performing defective bit analysis for mats, only arbitrary bit sequences within that word are selected. A multiplexer 51 is provided. This allows, for example, I
When O bit specification is made as 10 bit specification,
In the case of 4I10, FDO, FD4. FD8. FD12
. . , and the data is obtained at the input of the data processing section 43.

In the case of 8I/○, the data of FDO, FD8, . . . are sequentially read out. In this way, when analyzing other bit sequences, it is possible to sequentially read them in the same manner while switching this I10 bit designation.

Furthermore, all bits of the fail memory can be read out by simultaneously operating the buffers 52, 57, and 59 by specifying ALL, so that the output data FDO- of the fail memory 34 can be read.
FD15 is output at one time corresponding to data bus Do-D15. In addition, buffer 50.52゜53, 54.55
．． The outputs of 57, 58, and 59 are equivalent to an open circuit when the control signal is not active.

Above, we have taken up to 8-bit memory as an example of multi-bit configuration memory, but even in the case of larger memory such as 9 bits, the memory output for the increased memory block can be transferred via a buffer to 4I10 or 8■/○. This can be easily achieved by controlling in the same way as in the case of .

Furthermore, even when a plurality of fail memories 39 are used during multiple simultaneous tests, this is similarly possible by providing a pair of fail memories and data processing section 43. Alternatively, by allocating the outputs of a plurality of fail memories onto the data bus in parallel in one data processing unit, sequential analysis becomes possible.

〔Effect of the invention〕

As is clear from the above-mentioned embodiments, according to the present invention, it is possible to efficiently read out the test results of a multi-bit memory in a bit-by-bit manner, so that the analysis process for determining how to repair a defective bit can be done in a mat-compatible manner. This has the advantage that the analysis time can be significantly shortened because the repair judgment is easy.

[Brief explanation of the drawing]

Figure 1 is a circuit block diagram of a conventional memory test device;
The figure is a circuit block diagram showing one embodiment of the present invention, and FIG. 3 is a circuit configuration diagram showing the memory extraction section of FIG. 2 in detail. 1.21...Pattern generator, 2,22...Memory under test, 3.33...Comparator, 4,34...Fail memory, 5.35...Computer, 36... Data distributor, 37.49.51... Multiplexer, 38... Address shifter, 39... Memory selector, 40... Address distributor,
41...Memory extraction section, 42...Failure analysis section, 43
...Data processing unit, 44...Address generator. 45...Instruction register, 46.47.48...Bus switch, 50°52, 53.54.55.57.58.
59...Buffer, 56...Decoder, 60.61
...and gate, 62.63...or gate. Agent Patent Attorney Tadashi Akimoto Figure 1

Claims (1)

[Claims] In a semiconductor memory testing device, a test result in which one word of the memory under test has a plurality of bits is output to successive terminals of multiple fail memory blocks, and data of a specific bit series within the word is arbitrarily selected. The device is equipped with means for reading data in parallel corresponding to a plurality of bit configurations, and means for reading data in units of multiple bit widths regardless of the bit configuration width of the memory under test. 1. A memory testing device characterized in that it is configured to be able to read each bit of a multi-bit configuration memory corresponding to a mat unit at the time of reading.