JPH09147596A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device with a short test time. SOLUTION: A control part 1 accesses all addresses of a fail memory 34 by an address generation circuit 35 at a first analysis and at the same time stores the address of a faulty memory cell by an index memory 4 and accesses only an address stored at the index memory 4 at a second analysis or thereafter, thus reducing test time as compared with before where all addresses of the fail memory 34 were accessed even at a second analysis and thereafter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly to a semiconductor test apparatus which determines whether each memory cell of a semiconductor memory device is normal or defective and analyzes the determination result.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional semiconductor test apparatus, and FIG. 4 is a flow chart showing its operation.

Referring to FIG. 3, this semiconductor test apparatus is
The defect count unit 33 includes a control unit 31, a test unit 32, and a defect count unit 33. The defect count unit 33 includes a fail memory 34, an address generation circuit 35, a selector 36, a row mask memory 37, a column mask memory 38, AND gates 39, 40, and rows. A fail bit counter 41 and a column fail bit counter 42 are included.

The control unit 31 controls the entire semiconductor test apparatus, analyzes the counting result of the defect counting unit 33, and repairs the rows and columns to be repaired by the spare line of the semiconductor memory under test (hereinafter referred to as MUT) 30. To decide.

The test section 32 outputs a test signal including data, an address, a control signal and the like to the MUT 30 in accordance with the test program, writes / reads data to / from each memory cell of the MUT 30, and makes each memory cell normal. Or defective. Then, the test unit 32
Is the fail data of each memory cell based on the judgment result (“0” if normal, “1” if defective)
Together with the address of the memory cell, the fail memory 3
Give to 4.

The fail memory 34 includes a storage area corresponding to each memory cell of the MUT 30, and stores the fail data of the memory cell corresponding to the storage area of the address given by the test section 32. That is, fail memory 3
4 stores defective memory cell distribution information (fail bit map) of the MUT 30.

The address generation circuit 35 gives a read address to the fail memory 34 via the selector 36 at the time of failure analysis after the fail data of all the memory cells of the MUT 30 are stored in the fail memory 34. This address is also given to the mask memories 37 and 38 and the fail bit counters 41 and 42 at the same time. The selector 36 is
An address output from the test unit 32 is passed when the test unit 32 determines, and an address generation circuit 3 is used when a failure is analyzed.
The address output from 5 is passed.

The row mask memory 37 has a storage area corresponding to each memory cell of the MUT 30, and mask data for each memory cell ("0" for a memory cell included in a row determined to be repaired by a spare line). , And "1") for the other memory cells are stored in the corresponding storage areas. The column mask memory 38 has a storage area corresponding to each memory cell of the MUT 30, and mask data for each memory cell (“0” for a memory cell included in a column determined to be repaired by a spare line, "1") is stored in the corresponding storage area for memory cells other than.

The AND gate 39 is connected to the fail memory 34.
The AND signal of the fail data read from the row mask memory 37 and the mask data read from the row mask memory 37 is applied to the row fail bit counter 41. The AND gate 40 gives a logical product signal of the fail data read from the fail memory 34 and the mask data read from the column mask memory 38 to the column fail bit counter 42. That is, the AND gates 39 and 40 are connected to the mask memories 37 and 3 respectively.
When the mask data "1" is read from 8, the fail data is passed as it is, and when the mask data "0" is read from the mask memories 37 and 38, the fail data is converted to "0".

The row fail bit counter 41 performs an AND operation.
The number of defective memory cells (number of fail cells) for each row of the MUT 30 is counted based on the fail data “1” that has passed through the gate 39 and the address of the memory cell in which the fail data “1” is stored. The column fail bit counter 42 determines the MUT based on the fail data “1” that has passed through the AND gate 40 and the address of the memory cell in which the fail data “1” was stored.
The number of defective memory cells in each of the 30 columns is counted.

Next, the operation of this semiconductor test apparatus will be described. With reference to FIG. 4, the control unit 31 determines in step S
31, the mask memories 37 and 38 and the counter 4
Clear 1,42. Next, in step S32, the control unit 31 tests each memory cell of the MUT 30 by the test unit 32 and simultaneously stores the fail data of each tested memory cell in the fail memory 34.

After storing the fail data of all the memory cells of the MUT 30 in the fail memory 34, the controller 31
In step S33, the address generation circuit 35 accesses each storage area of the fail memory 34 in the order of addresses to read the fail data stored in each storage area.

Next, in step S34, the control unit 31 causes the counters 41 and 42 to perform defective memory for each row and column based on the fail data read from the fail memory 34 and the mask data read from the mask memories 37 and 38. Count the number.

Next, the control unit 31 determines in step S35 whether or not the reading of the fail data from the fail memory 34 is completed. If not completed, the process returns to step S33, and if completed, the step S36. In, the number of defective memory cells for each row and column counted by the counters 41 and 42 is analyzed, and the spare line determines the row and column to be relieved.

Next, the control unit 31 determines in step S37 whether or not the repair of all defective memory cells is completed. If completed, the test is ended, and if not completed, the repair is carried out in step S38. It is determined whether or not a spare line remains. Then, if no spare line remains, the control unit 31 ends the test, and if a spare line remains, in step S39, the mask data "in the storage area corresponding to the repair row or column of the mask memories 38, 39" After writing "0", step S3 is performed again.
Return to 3.

That is, steps S33 to S39 are repeated until all the defective memory cells of the MUT 30 are repaired by the spare line or the spare line is exhausted, and the test for the MUT 30 is completed.

[0017]

As described above, in the conventional semiconductor test apparatus, since the entire storage area of the fail memory 34 is accessed many times to read the fail data, the memory of the MUT 30 is read. There is a problem that the test time increases as the number of cells increases.

Therefore, a main object of the present invention is to provide a semiconductor test apparatus having a short test time.

[0019]

A semiconductor testing device according to the present invention is a semiconductor testing device for judging whether each memory cell of a semiconductor memory device is normal or defective and analyzing the judgment result. 1 storage means, 1st reading means, 2nd
Storage means, second reading means, and analysis means. The first storage means stores the determination result of each memory cell of the semiconductor memory device in the order of the memory cell address. First
Read means reads the determination results of all the memory cells of the semiconductor memory device from the first storage means during the first analysis. The second storage means stores the address of the memory cell when the determination result of the memory cell read by the first reading means from the first storage means is defective. Second
The reading means reads the address of the memory cell from the second storage means during the second and subsequent analyzes, and reads the determination result of the memory cell at the read address from the first storage means.
The analysis means analyzes the read results of the first and second read means and determines the row and column to be repaired by the spare line of the semiconductor memory device.

In this semiconductor test apparatus, the determination results of all the memory cells are read out at the time of the first analysis and the addresses of the defective memory cells are stored, and at the time of the second and subsequent analyses, the memory cell of the stored address, that is, Only the determination result of the defective memory cell is read. Therefore, the test time can be shortened as compared with the conventional method in which the determination results of all the memory cells are read during the second and subsequent analyzes.

Also preferably, the analysis means includes counting means and determination means. The counting means counts the number of defective memory cells for each row and column of the semiconductor memory device based on the reading results of the first and second reading means. The determining means determines a row and a column to be repaired by the spare line of the semiconductor memory device based on the counting result of the counting means. This allows
The analysis means is easily configured.

Further preferably, third storage means and conversion means are further provided. The third storage means stores the addresses of the memory cells included in the row and column for which the repair by the spare line has been determined by the analysis means. The converting means causes the second reading means to cause the first storing means to respond in response to the address read from the second storing means by the second reading means matching the address stored in the third storing means. The determination result of the memory cell read from is converted from defective to normal and given to the analyzing means. As a result, the defective memory cell repaired by the spare line is assumed to have become a normal memory cell.

[0023]

1 is a block diagram showing the configuration of a semiconductor test apparatus according to an embodiment of the present invention, FIG.
Is a flowchart showing the operation.

Referring to FIG. 1, this semiconductor test apparatus is
The control unit 1, the test unit 32, and the defect counting unit 2 are provided, and the defect counting unit 2 includes the counter 3, the index memory 4, the selector 5, the fail memory 34, and the address generation circuit 3.
5, row mask memory 37, column mask memory 38, AND
It includes gates 39 and 40, a row fail bit counter 41 and a column fail bit counter 42. Test section 3
2, the fail memory 34, the address generation circuit 35, the mask memories 37 and 38, the AND gates 39 and 40, and the fail bit counters 41 and 42 are the same as those described with reference to FIG.

The counter 3 counts the fail data "1" read from the fail memory 34 at the time of the first analysis, and gives the write address to the index memory 4 by the count value. Also, the counter 3 has a second
The read address is given to the index memory 4 at the time of the subsequent analysis.

The index memory 4 outputs the address output from the address generation circuit 35 to the address designated by the counter 3 in response to the read of the fail data "1" from the fail memory 34 during the first analysis. Memorize Therefore, the address (fail cell address) of the defective memory cell is sequentially stored in the index memory 4. Also, the index memory 4
Applies the stored defective memory cell address as a read address to the fail memory 34 through the selector 5 during the second and subsequent analyzes. This address is also given to the mask memories 37 and 38 and the counters 41 and 42 at the same time.

The selector 5 allows the address output from the test unit 32 to pass when the test unit 32 makes a determination, and
At the time of the second analysis, the address output from the address generation circuit 35 is passed, and at the time of the second and subsequent analyses, the address read from the index memory 4 is passed.

Next, the operation of this semiconductor test apparatus will be described. Referring to FIG. 2, the control unit 1 performs step S1.
In the mask memories 37 and 38 and the counter 41,
Clear 42. Next, in step S2, the control unit 1 tests each memory cell of the MUT 30 by the test unit 32 and, at the same time, stores the fail data of each tested memory cell in the fail memory 34.

After storing the fail data of all the memory cells of the MUT 30 in the fail memory 34, the control section 1 accesses each memory area of the fail memory 34 by the address generation circuit 35 in step S3 and stores them in each memory area. The read fail data is read.

Next, the control unit 1 proceeds to step S4.
Based on the fail data read from the fail memory 34 and the mask data read from the mask memories 37 and 38, the number of defective memory cells for each row and column is counted by the counters 41 and 42. Fail memory 3 at this time
When the fail data read from 4 is “1”, the fail cell address output from the address generation circuit 35 is stored in the address of the index memory 4 designated by the counter 3.

Next, the control unit 1 determines in step S5 whether or not the reading of the fail data from the fail memory 34 is completed. If not completed, the process returns to step S3, and if completed, the step S6. In, the number of defective memory cells for each row and column counted by the counters 41 and 42 is analyzed, and the spare line determines the row and column to be relieved.

Then, the control section 1 determines whether or not the repair of all the defective memory cells is completed in step S7. If the repair is completed, the test is ended, and if not completed, the repair is carried out in step S8. It is determined whether or not a spare line remains. Then, if no spare line remains, the control unit 1 ends the test, and if a spare line remains, in step S9, the mask data "in the storage area corresponding to the repair row and column of the mask memories 38 and 39" is written. Write "0".

Next, in step S10, the control unit 1 accesses each storage area of the index memory 4 by the counter 3 in order of address to read the fail cell address, and gives the read fail cell address to the fail memory as a read address to fail. Read the data. Next, in step S11, the control unit 1 outputs the fail data read from the fail memory 34 and the mask memory 3 to each other.
Based on the mask data read from 7, 38,
Count the number of defective memory cells in each column.

Next, the control unit 1 determines in step S12 whether or not the reading of the fail data from the fail memory 34 is completed. If the reading is not completed, the process returns to step S10 again, and if it is completed, Step S6 again
Return to

That is, steps S6 to S12 are repeated until all the defective memory cells of the MUT 30 are repaired by the spare line or there is no spare line, and the test for the MUT 30 is completed.

As described above, in this embodiment, the first
The fail cell address is stored in the index memory 4 at the time of the second analysis, and only the fail data of the fail cell address is read at the time of the second and subsequent analyses. Therefore, the test time is shortened as compared with the conventional case in which the fail data of all the addresses are read even in the second and subsequent analyzes.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor test apparatus according to an embodiment of the present invention.

FIG. 2 is a flow chart showing an operation of the semiconductor test device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional semiconductor test device.

FIG. 4 is a flowchart showing an operation of the semiconductor test device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 control unit, 2 defect counting unit, 3 counter, 4 index memory, 5 selector, 30 semiconductor memory under test (MUT), 31 control unit, 32 test unit, 33
Defect counting section, 34 fail memory, 35 address generation circuit, 36 selector, 37 row mask memory, 38
Column mask memory, 39, 40 AND gate, 41 row fail bit counter, 42 column fail bit counter.

Claims (3)

[Claims] 1. A semiconductor test apparatus for determining whether each memory cell of a semiconductor memory device is normal or defective and analyzing the determination result, wherein the determination result of each memory cell of the semiconductor memory device is a memory cell. Storage means for storing in order of the address, first reading means for reading the determination results of all the memory cells of the semiconductor memory device from the first storage means at the time of the first analysis, the first storage means Second storage means for storing the address of the memory cell in response to the result of the determination of the memory cell read by the first reading means being defective, the second storage during the second and subsequent analyzes. A second reading means for reading the address of the memory cell from the means, and reading the determination result of the memory cell at the read address from the first storage means;
And a analyzing unit for analyzing read results of the first and second reading units to determine a row and a column to be repaired by a spare line of the semiconductor memory device. 2. The analyzing means, based on the reading results of the first and second reading means,
Counting means for counting the number of defective memory cells in each row and column of the semiconductor memory device, and determining means for determining the row and column to be relieved by the spare line of the semiconductor memory device based on the counting result of the counting means. The semiconductor test apparatus according to claim 1, comprising: 3. A third storage means for storing the address of a memory cell included in a row or a column for which repair by a spare line is determined by the analysis means, and the second read means by the second read means. When the address read from the storage means matches the address stored in the third storage means, the determination result of the memory cell read from the first storage means by the second read means is displayed. 3. The semiconductor test apparatus according to claim 1, further comprising a conversion unit that converts a defect into a normal signal and applies the normal analysis result to the analysis unit.