JP2792327B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a plurality of memory blocks having different word lengths.

[0002]

2. Description of the Related Art In recent years, the technology of semiconductor integrated circuits has been remarkably developed, and the scale and complexity of semiconductor integrated circuit devices have been accelerating. Along with this, one of the factors that determines the cost and reliability of a product is to efficiently perform a function test of a semiconductor integrated circuit device and detect a defect at a high rate.

Further, the scale of the semiconductor integrated circuit device has been increased,
With the progress of compounding, the difficulty of failure analysis has also increased.

A circuit division method is often used as a method for efficiently performing a function test of this semiconductor integrated circuit device, detecting a defect at a high rate, and easily performing a defect analysis.
This circuit partitioning method uses a RAM (random access memory) or ROM mounted on a large-scale semiconductor integrated circuit device.
(Read-only memory) or a set of circuits having a certain set of functions is divided into function blocks, and the function of each function block is verified separately from the function verification of the entire semiconductor integrated circuit device It is.

FIG. 5 shows a first specific example of a semiconductor integrated circuit device to which the circuit division method is applied.

This semiconductor integrated circuit device has four memory blocks MB1 to MB4. Each of these memory blocks MB1 to MB4 has normal data (IN1 to IN4) having a predetermined word length transmitted in a bit-parallel manner. Test data of the same word length as the corresponding normal data (TIN
1 to TIN4) (SL)
1 to SL4) and corresponding selectors (SL1 to SL4)
And memory circuits (MC1 to MC4) for storing the output data and reading the stored data.

Normal data IN1 to IN4 are input terminals T
The signal is input from the MI in a bit parallel manner, and is input to the selector of the corresponding memory block via the data bus 2a. Normal data OUT1 to OUT4 read from each of the memory blocks MB1 to MB4 are output to the outside from the output terminal TMO via the data bus 2b.

The test data TIN1 to TIN4 are
These are input from test data input terminals provided correspondingly to these, and transmitted to the selectors of the corresponding memory blocks.

Further, test data TOUT1-TOUT4 read from each of memory blocks MB1-MB4.
Are output to the outside in bit parallel from test data output terminals provided correspondingly.

In the first example, the test data TI
N1 to TIN4 and read data TOU for test
Since T1 to TOUT4 are input and output through test data input terminals and test data output terminals provided respectively, the number of terminals is increased.

Therefore, in a second example of the conventional semiconductor integrated circuit device shown in FIG. 6, an input data selection circuit 4 and an output selection circuit 5 are provided to reduce the number of test data input terminals and test data output terminals. Has been reduced.

Next, a method for testing these semiconductor integrated circuit devices will be described.

First, a test of the entire semiconductor integrated circuit device is performed using normal data input terminals and data output terminals. This test is generally a test for testing the functions of the entire semiconductor integrated circuit device, and does not test the detailed functions of the individual memory blocks MB1 to MB4. Tests such as a connection between the MBs 4 and an interface with the outside are mainly performed.

After the function test of the entire semiconductor integrated circuit device,
A detailed test of each of the memory blocks MB1 to MB4 is performed. A detailed test of each of the memory blocks MB1 to MB4 is performed directly from the outside.
, Test data (TIN1 to TIN1) corresponding to
N4) is input, and the output data TOUT1 to TOUT4 of each memory block based on the input is externally determined.
The array of test data in this case is generally called a test pattern.

FIG. 7 shows the structure of a test pattern for sequentially testing each of the memory blocks MB1 to MB4. Test patterns PTIN1 to PTIN4 are provided corresponding to the memory blocks MB1 to MB4, respectively.
To the test pattern PTIN1 to PTIN4 of MB4. In general, a memory block test is performed by holding a “1” or “0” state, inter-bit interference,
Various tests such as inter-byte interference are required. Further, it is necessary to perform a test for the storage capacity. Current,
In order to test a memory block having a capacity of 1000 bytes, a test pattern of about 20,000 data is required. At present, semiconductor integrated circuit devices are moving toward higher integration and higher speeds, and the number of built-in memory blocks is expected to increase dramatically in the future. Inevitably increase.

[0016]

In the first example, the conventional semiconductor integrated circuit device described above has a structure in which each memory block MB is used.
The configuration is such that the test data of 1 to MB4 is input / output by the corresponding test data input terminal and test data output terminal, so that the number of terminals increases, and each memory has a disadvantage. Block M
Since it is necessary to set a test pattern for B1 to MB4, the performance of a test apparatus (hereinafter referred to as an LSI tester) for testing the test pattern increases due to an increase in the number of data of the test pattern. The tester cannot test, and the place where the test can be performed is limited. Further, an increase in the number of test patterns directly leads to an increase in test time, which causes a problem that the productivity (throughput) of the semiconductor integrated circuit device deteriorates. In the second example, the number of test data input terminals and test data output terminals can be reduced because the input data selection circuit 4 and the output selection circuit 5 are provided, but the test patterns are the same as in the first example. There is a problem.

An object of the present invention is to reduce the number of test terminals and the number of test pattern data,
It is an object of the present invention to provide a semiconductor integrated circuit device capable of eliminating the restriction of the I tester and improving the productivity.

[0018]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention operates one of normal data having a predetermined word length transmitted in a bit parallel manner and test data having a word length equal to this data. A plurality of memory blocks each including a selector to be selected according to a mode, a memory circuit for storing output data of the selector and reading the stored data, and a maximum word among word lengths of data transmitted to each of the memory blocks Input data distribution circuit for inputting test data having a word length equal to the data length, converting the test data into test data equal to the word length of the data in each memory block, and transmitting the data to the selector of the corresponding memory block A normal output circuit that outputs normal data read from each of the memory blocks to the outside; And a data output circuit for testing for outputting data for read test to the outside.

Further, the test data output circuit compares the test data read from each memory block with the corresponding verification data and outputs a comparison result signal indicating whether or not they match. It comprises a comparison circuit.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor integrated circuit device shown in FIG. 5 in that each memory block MB1
To test data TIN having a word length equal to the maximum word length among the word lengths of the data transmitted to the memory blocks MB1 to MB4.
Test data TIN1 to TINT equal to the word length of the data
An input data distribution circuit 1 that transmits the data to the selector of the corresponding memory block at IN4 is provided.
As shown in FIG. 2, the input data distribution circuit 1 includes a register 11 for holding data having a maximum word length, and outputs the test data TIN1 to TIN4 from the output of the register 11.
Is generated.

By providing this input data distribution circuit 1, the number of test data input terminals can be greatly reduced. As shown in FIG. 3, test patterns PTIN1 to PTIN4 of each memory block are overlapped with each other, and the portions overlapping each other have the same data as shown in FIG.
Since the test pattern PTIN can be set as TIN, the number of data of the entire test pattern PTIN can be reduced to about 1 / the number of memory blocks of the conventional example.

FIG. 4 is a block diagram of a second embodiment of the present invention.

In this embodiment, a test data output circuit is provided with a verification data input terminal for inputting verification data for verifying test data TOUT1 to TOUT4 read from each of the memory blocks MB1 to MB4. A comparison circuit 3 that compares test data TOUT1 to TOUT4 read from each of memory blocks MB1 to MB4 with corresponding verification data and outputs a comparison result signal RST indicating whether or not they match. Is provided.

With this configuration, the number of terminals related to the output of the read test data can be significantly reduced.

In this embodiment, the verification data input terminal is newly provided. However, the verification data input terminal can be used also as the test data input terminal. In this case, the number of test terminals can be further reduced.

[0028]

As described above, according to the present invention, test data having a word length equal to the maximum word length of the word length of data transmitted to each memory block is input, and the test data is stored in each memory block. By providing an input data distribution circuit for providing test data equal to the word length of the memory block data and transmitting the data to the corresponding memory block selector, the number of test data input terminals can be reduced, In addition, since the test pattern of each memory block can be superimposed to form one test pattern, the number of test pattern data can be significantly reduced, thus eliminating the limitations of the LSI tester and improving the productivity. There is an effect that can be.

Further, by providing a comparison circuit for comparing the test data read from each memory block with the corresponding verification data and outputting a comparison result signal indicating whether or not the data coincide with each other, There is an effect that the number of test data output terminals can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the input data distribution circuit of the embodiment shown in FIG.

FIG. 3 is a data layout diagram of a test pattern used in the embodiment shown in FIG. 1;

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a first example of a conventional semiconductor integrated circuit device.

FIG. 6 is a block diagram of a second example of a conventional semiconductor integrated circuit device.

FIG. 7 is a data layout diagram of a test pattern for the semiconductor integrated circuit device shown in FIGS. 5 and 6;

[Explanation of symbols]

 Reference Signs List 1 input data distribution circuit 2a, 2b data bus 3 comparison circuit 4 input data selection circuit 5 output selection circuit MB1 to MB4 memory block MC1 to MC4 memory circuit SL1 to SL4 selector

Claims (2)

(57) [Claims] 1. A selector for selecting one of normal data having a predetermined word length transmitted in a bit parallel manner and test data having a word length equal to this data in accordance with an operation mode, and outputting data of the selector. A plurality of memory blocks each having a memory circuit for storing and reading stored data, and test data having a word length equal to the maximum word length of the word lengths of data transmitted to each of the memory blocks are inputted. An input data distribution circuit for converting the test data into test data equal to the word length of the data in each of the memory blocks, and transmitting the test data to the selectors of the corresponding memory blocks; and normal data read from each of the memory blocks. A normal output circuit that outputs
A test data output circuit for outputting test data read from each of the memory blocks to the outside. 2. A test data output circuit compares test data read from each memory block with corresponding verification data and outputs a comparison result signal indicating whether or not they match. 2. The semiconductor integrated circuit device according to claim 1, comprising a comparison circuit.