JPH05314794A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve productivity by reducing terminal numbers for a test, while reducing data numbers of a test pattern, and eliminating restriction for a LSI tester. CONSTITUTION:An input data distribution circuit 1 is provided, wherein, data for a test having equal word length to the longest word length among data word length transmitted to each memory block MB1-MB4 is inputted, this data for a test is made to data for a test having equal word length to data word length of each memory block MB1-MB4, and transmitted respectively to selectors SL1-SL4 corresponding to each memory block. A test pattern is to be one test pattern in which test patterns of each memory block MB1-MB4 are superposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a plurality of memory blocks having different word lengths.

[0002]

2. Description of the Related Art In recent years, the technological development of semiconductor integrated circuits has been remarkable, and the scale-up and integration of semiconductor integrated circuit devices have accelerated. Along with this, efficient function testing of semiconductor integrated circuit devices and detection of defects at a high rate are one of the factors that determine the cost and reliability of products.

Further, the scale of the semiconductor integrated circuit device is increased,
With the progress of compounding, the difficulty level of failure analysis is increasing.

A circuit division method is often used as a method for efficiently performing a functional test of this semiconductor integrated circuit device, detecting a high percentage of defects, and performing a defect analysis easily.
This circuit division method is applied to a RAM (random access memory) or ROM mounted on a large-scale semiconductor integrated circuit device.
(Read-only memory), or a group of circuits having a certain set of functions is divided into functional blocks, and the function of each functional block is verified separately from the function verification of the entire semiconductor integrated circuit device. Is.

FIG. 5 shows a concrete first example of a semiconductor integrated circuit device to which the circuit division method is applied.

This semiconductor integrated circuit device has four memory blocks MB1 to MB4, and each of these memory blocks MB1 to MB4 has normal data (IN1 to IN4) of a predetermined word length transmitted in bit parallel and The test data (TIN with the same word length as the corresponding normal data)
1 to TIN4) select selector (SL
1 to SL4) and corresponding selectors (SL1 to SL4)
Corresponding to the memory circuits (MC1 to MC4) for storing the output data of and reading the stored data.

Normal data IN1 to IN4 are input terminals T
It is inputted in bit parallel from MI and inputted to the selector of the corresponding memory block via the data bus 2a. Ordinary data OUT1 to OUT4 read from the memory blocks MB1 to MB4 are output to the outside from the output terminal TMO via the data bus 2b.

The test data TIN1 to TIN4 are
These are input from test data input terminals provided corresponding to these, respectively, and transmitted to the selectors of the corresponding memory blocks.

Further, the test data TOUT1 to TOUT4 read from the memory blocks MB1 to MB4.
Are output to the outside in bit parallel from the test data output terminals provided correspondingly.

In this first example, the test data TI
N1 to TIN4 and the read test data TOU
Since T1 to TOUT4 are input / output by the test data input terminal and the test data output terminal provided corresponding to each other, the number of terminals increases.

Therefore, in the second example of the conventional semiconductor integrated circuit device shown in FIG. 6, the input data selection circuit 4 and the output selection circuit 5 are provided, and the number of test data input terminals and test data output terminals is set. It is decreasing.

Next, a method of testing these semiconductor integrated circuit devices will be described.

First, using the usual data input terminal and data output terminal, the entire semiconductor integrated circuit device is tested. This test is generally a test that can test the functions of the entire semiconductor integrated circuit device, and does not test the detailed functions of the individual memory blocks MB1 to MB4. Tests such as connection between MB4 and interface with the outside are mainly performed.

After the functional test of the entire semiconductor integrated circuit device,
A detailed test of the individual memory blocks MB1 to MB4 is performed. A detailed test of the individual memory blocks MB1 to MB4 is performed by directly externally testing the memory blocks MB1 to MB4.
For test (TIN1 to TI
N4) is input, and the output data TOUT1 to TOUT4 of each memory block based on the input N4) are externally determined.
The enumeration of test data in this case is generally called a test pattern.

FIG. 7 shows the structure of a test pattern for sequentially testing each of the memory blocks MB1 to MB4. Test patterns PTIN1 to PTIN4 are provided corresponding to the memory blocks MB1 to MB4, and the data number of the entire test pattern is the same as that of each memory block MB1.
Is the sum of the data numbers of the test patterns PTIN1 to PTIN4 of MB4. Generally, a memory block test includes a "1" and "0" state holding test, inter-bit interference,
Various tests such as inter-byte interference are required. Further, it is necessary to test the storage capacity. Current,
A test pattern of about 20000 data is required to test a memory block having a capacity of 1000 bytes. Currently, semiconductor integrated circuit devices are advancing toward higher integration and higher speed, and the number of built-in memory blocks is expected to increase dramatically in the future. The increase is inevitable.

[0016]

In the first example, the above-described conventional semiconductor integrated circuit device has the memory blocks MB.
Since the test data of 1 to MB4 are input and output by the test data input terminal and the test data output terminal respectively provided correspondingly, there is a drawback that the number of terminals is increased, and each memory is Block M
Since it is necessary to set a test pattern for B1 to MB4, an increase in the number of data of the test pattern requires improvement in the performance of a test device (hereinafter referred to as an LSI tester) that tests the test pattern, which is less than the performance. The tester will not be able to test, and the places that can be tested will be limited. Furthermore, the increase in the number of test patterns leads to an increase in the test time as it is, and there is a problem that the productivity (throughput) of the semiconductor integrated circuit device deteriorates. Also, in the second example, since the input data selection circuit 4 and the output selection circuit 5 are provided, the number of test data input terminals and test data output terminals can be reduced, but the test pattern is the same as in the first example. There is a problem.

An object of the present invention is to reduce the number of test terminals and the number of test pattern data,
It is an object of the present invention to provide a semiconductor integrated circuit device which can improve productivity by eliminating the restriction of the I tester.

[0018]

A semiconductor integrated circuit device according to the present invention operates one of normal data of a predetermined word length transmitted in bit parallel and test data of a word length equal to this data. A plurality of memory blocks each having a selector that selects according to the mode and a memory circuit that stores the output data of the selector and reads the stored data, and the maximum word of the word lengths of the data transmitted to these memory blocks. An input data distribution circuit for inputting test data having a word length equal to the length and converting the test data into test data equal to the word length of the data of each memory block and transmitting the test data to the selectors of the corresponding memory blocks. A normal output circuit for outputting normal data read from each of the memory blocks to the outside; And a data output circuit for testing for outputting data for read test to the outside.

Further, the test data output circuit compares the test data read from each memory block with the corresponding verification data and outputs a comparison result signal indicating whether or not these match. It is configured to include a comparison circuit.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention.

This embodiment differs from the conventional semiconductor integrated circuit device shown in FIG. 5 in that each memory block MB1
To MB4, the test data TIN having a word length equal to the maximum word length of the word lengths of the data transmitted is input, and the test data TIN is input to each of the memory blocks MB1 to MB4.
Test data TIN1 to T equal to the word length of the data
The point is that the input data distribution circuit 1 which is set to IN4 and is transmitted to the selector of the corresponding memory block is provided.
As shown in FIG. 2, the input data distribution circuit 1 is provided with a register 11 for holding the data of the maximum word length, and from the output of the register 11, the test data TIN1 to TIN4.
Is configured to generate.

By providing this input data distribution circuit 1, the number of test data input terminals can be greatly reduced. In addition, as shown in FIG. 3, the test pattern is obtained by superposing the test patterns PTIN1 to PTIN4 of each memory block, and by overlapping the mutually overlapping portions with the same data, the entire test pattern P
Since it can be TIN, the number of data of the entire test pattern PTIN can be reduced to about 1 / the number of memory blocks of the conventional example.

FIG. 4 is a block diagram of the second embodiment of the present invention.

In this embodiment, a test data output circuit is provided with a verification data input terminal for inputting verification data for verifying the test data TOUT1 to TOUT4 read from each of the memory blocks MB1 to MB4. A comparison circuit 3 that is provided to compare the test data TOUT1 to TOUT4 read from each of the memory blocks MB1 to MB4 with the corresponding verification data and output a comparison result signal RST indicating whether or not these match. Is provided.

With this structure, the number of terminals related to the output of the read test data can be significantly reduced.

In this embodiment, a verification data input terminal is newly provided, but it can also be used as a test data input terminal. In this case, the number of test terminals can be further reduced.

[0028]

As described above, according to the present invention, the test data having the word length equal to the maximum word length of the word lengths of the data transmitted to each memory block is input, and the test data is input to each memory block. The number of test data input terminals can be reduced by providing an input data distribution circuit that transmits test data equal to the word length of the memory block to the selectors of the corresponding memory blocks. Moreover, since the test patterns of each memory block can be overlapped to form one test pattern, the number of data of the test patterns can be significantly reduced. Therefore, the constraint of the LSI tester can be eliminated and the productivity can be improved. There is an effect that can be.

Further, by providing a comparison circuit which compares the test data read from each memory block with the corresponding verification data and outputs a comparison result signal indicating whether or not they match, This has the effect of reducing the number of test data output terminals.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an input data distribution circuit of the embodiment shown in FIG.

FIG. 3 is a data layout diagram of a test pattern used in the embodiment shown in FIG.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a first example of a conventional semiconductor integrated circuit device.

FIG. 6 is a block diagram of a second example of a conventional semiconductor integrated circuit device.

FIG. 7 is a data layout diagram of test patterns for the semiconductor integrated circuit device shown in FIGS. 5 and 6;

[Explanation of symbols]

 1 Input Data Distribution Circuit 2a, 2b Data Bus 3 Comparison Circuit 4 Input Data Selection Circuit 5 Output Selection Circuit MB1-MB4 Memory Block MC1-MC4 Memory Circuit SL1-SL4 Selector

Claims (2)

[Claims] 1. A selector for selecting one of normal data having a predetermined word length transmitted in bit parallel and test data having a word length equal to this data according to an operation mode, and output data of the selector. A plurality of memory blocks each having a memory circuit for storing and reading the stored data and test data having a word length equal to the maximum word length of the word lengths of the data transmitted to these memory blocks are input. An input data distribution circuit for converting the test data into test data having the same word length as the data length of each memory block and transmitting it to the selector of the corresponding memory block, and normal data read from each memory block. A normal output circuit that outputs the
A test data output circuit for outputting test data read from each memory block to the outside, a semiconductor integrated circuit device. 2. A test data output circuit compares the test data read from each memory block with the corresponding verification data and outputs a comparison result signal indicating whether or not these match. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device comprises a comparison circuit.