JPH0619803A - Memory circuit device - Google Patents

Abstract

PURPOSE:To considerably reduce the number of test pattern data so as to efficiently conduct a test in a short time for conducting the test of a memory circuit device including plural memory blocks having different bit lengths and word lengths. CONSTITUTION:The blocks are composed of the bit length and the word length, which are respectively equal to the maximum bit length and the maximum word length, among the bit lengths and the word lengths of respective memories 8-11 in a test pattern storage circuit 24. The words of the storage test pattern of the storage circuit 24 are simultaneously outputted to the respective memories by adjusting them to the bit lengths of the respective memories by an input signal distribution circuit 25. Thus, the total number of the words of the test pattern is reduced to about 1/4 (when the number of the memories 8-11 is set to be four) compared to a conventional case.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a memory circuit device, and more particularly to a semiconductor integrated circuit device including a plurality of memory blocks having different bit lengths and word lengths.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuit technology has been remarkable, and the scale-up and integration of semiconductor integrated circuits have accelerated. Along with this, efficient detection of the functional test of the semiconductor integrated circuit and detection of defects at a high rate are one of the factors that determine the cost and reliability of the product. Further, as the scale of semiconductor integrated circuits becomes larger and the integration of semiconductor integrated circuits progresses, the difficulty level of failure analysis becomes higher.

A circuit division method is often used as a method for efficiently performing this functional test, detecting defects at a high rate, and easily performing defect analysis. This circuit division method is
RAM (random access
Memory), ROM (Read Only Memory), or a set of circuits having a certain set of functions is divided into functional blocks, respectively, and separately from the verification of the functions of the entire circuit,
The function of each functional block is verified. A specific example of the circuit division method will be described with reference to FIGS.

In FIG. 5, memory blocks 4, 5,
Input signals 16, 17, and
18, 19 and memory block test input signals 46, 4 when testing each memory block 4, 5, 6, 7.
7, 48, 49 and selectors 12, 13, 14, 15
Are selected respectively by the input signals and input to the memory circuits 8, 9, 10, and 11.

Further, the output signals 20, 21, 22, 23 of the memory circuits 8, 9, 10, 11 are provided in the memory block test provided for use in the test separately from the internal bus 3 connected in the normal operation. Output signal bus 50,5
It is output to 1, 52 and 53, respectively. In the circuit configuration of this conventional example, in addition to the input signal bus 1 and the output signal bus 2 in normal use, test input signal buses 46, 47, used for testing the memory blocks 4, 5, 6, 7 are provided. Four
8, 49 and test output signal buses 50, 51, 52,
53 is provided.

When testing each memory block, a test signal is directly input from the outside to the test input signal buses 46 to 49, and the output signals from the test output signal buses 50 to 53 of each memory block are externally output. The determination is made to determine whether or not each memory block is operating normally. In this example, it is necessary to provide an input terminal and an output terminal for a test for each memory block, whereas in FIG.
In the conventional example, the memory block test input terminal and the memory block test output terminal are shared by each memory block.

Input signal bus 54 for memory block test
The test signal of 1 is divided into each memory block 4, 5, 6, 7 by the input selection circuit 56. Input selection circuit 56
Outputs a test input signal only to the memory block to be tested. On the other hand, the output signal buses 20, 21, 22, 23 of each memory block during the memory block test are input to the output selection circuit 57. The output selection circuit 57 selects the output of the memory block to be tested and outputs it as the memory block test output signal bus 55 to the outside.

In the conventional example of FIG. 6, the number of memory block test input terminals and output terminals can be reduced as compared with the conventional example of FIG. Furthermore, there is also a method of sharing the input terminal and output terminal used in the normal state with the test input terminal and output terminal used in the test, but the description thereof will be omitted here.

A method of testing the semiconductor memory circuit device having the conventional configuration shown in FIGS. 5 and 6 will be described. First, a test of the entire semiconductor integrated circuit device is performed using normal input signal and output signal terminals. The test at that time is generally a test that can test the function of the entire semiconductor memory circuit device, and is not a test that can test the detailed function of each memory block. Tests such as connection between individual memory blocks and external interface are mainly performed.

After the functional test of the entire semiconductor memory circuit device, a detailed test of individual memory blocks is performed. A detailed test of each memory block is performed by directly inputting a signal from the outside to each memory block and externally determining the output signal of each memory block. A list of test signals in that case is generally called a test pattern. FIG. 7 shows the configuration of the test pattern when there are four memory blocks.

In FIG. 7, the test patterns 39, 40, 41, 42 of the memory blocks are different from each other, and the memory circuits 8, 5, 6, 7 of the memory blocks 4, 5, 6, 7 of FIGS. The pattern corresponds to 11 bit lengths and 11 word lengths. Therefore, the total number of test patterns is 3 for each memory block.
It is the sum of 9, 40, 41 and 42.

As described above, in the conventional semiconductor memory circuit device, the total number of test patterns used for testing all the built-in memory blocks is the sum of the test pattern numbers of the built-in memory blocks. Generally, a memory block test is a holding test of "1" and "0" states,
Various tests such as inter-bit interference, inter-byte interference, etc. are required. Further, it is necessary to test the storage capacity. Currently, about 20,000 test patterns are required to test a memory block having a capacity of 1000 bytes.

Currently, semiconductor memory circuit devices are highly integrated.
It is considered that the number of built-in memory blocks will increase dramatically in the future as the speed increases, and thus the number of test patterns required for testing memory blocks is inevitable. Due to the increase in the number of test patterns, it is necessary to improve the performance of the test equipment that tests them (hereinafter referred to as the LSI tester), and a tester that does not meet the required performance cannot test. It Furthermore, an increase in the number of test patterns directly leads to an increase in test time, which leads to a problem of productivity (throughput) of this integrated circuit device.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory circuit device in which there is no tester restriction due to the upper limit of the number of test patterns when testing a memory having a plurality of memory blocks and the productivity is improved. It is in.

[0015]

A memory circuit device according to the present invention has a plurality of memory circuits having different bit lengths and word lengths, and a maximum bit length and a maximum word length of the memory circuits, respectively. Test pattern storage means storing preset test pattern data and each test pattern word in the test pattern storage means are converted into a bit length corresponding to each bit length of the memory circuit, and then converted to a corresponding memory circuit. Signal distribution means for simultaneously distributing and supplying as the test input signal of.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The same parts as those in FIGS. In the figure,
During normal use, the input signal 1 is input to the memory blocks 4, 5, 6, and 7 through the internal signal bus 3.
Each of the memory blocks 4, 5, 6, 7 has a memory circuit 8, 9, 1 which performs the function expected of the original memory block.
0, 11 and normal input signals 16, 17,
The selectors 12, 13, 14, and 15 for selecting 18 or 19 or input signals 30, 31, 32, and 33 at the time of testing each memory block are respectively configured.

Further, a memory block test signal generating circuit 34 is provided, and this circuit 34 stores a test pattern which stores a memory block test input signal 35 which is input to test the functions of a plurality of memory blocks. A memory circuit 24 and an input signal distribution circuit 25 for commonly and simultaneously inputting a memory block test input signal 35 output from the test pattern memory circuit 24 to each of the plurality of memory blocks are included.

The memory block test input signal 35 is
The input signal distribution circuit 25 adjusts the input signals 30, 31, 32, 3 for each bit length according to the bit length of each memory block incorporated in the semiconductor memory integrated circuit.
3 is supplied to the memory blocks 4, 5, 6, and 7, respectively.

The memory blocks 4, 5, 6, 7 are operated by the input test input signals 30, 31, 32, 33, respectively, and the result is output as the memory block test output signal 2.
6, 27, 28 and 29 are output respectively. The memory block test output signals 26, 27, 28, and 29 are measured by an external tester of the semiconductor memory integrated circuit device, and the quality of each memory block is determined.

Next, the features of this embodiment, including the operation of the input signal distribution circuit 25, will be described with reference to FIGS.

FIG. 2 is a schematic diagram of the operating mechanism of the input signal distribution circuit 25. Although the memory block functions have different bit lengths and word lengths, basic control can be shared. Therefore, if a test pattern signal corresponding to the bit length of each memory block is supplied to each memory block, the number of necessary signals becomes the maximum bit length in each memory block. In the example of FIG. 1, since the bit length of the memory block 4 is the maximum, the test pattern signal is set to the bit length of this memory block 4.

Therefore, the test pattern (corresponding to one word) for the maximum bit length is derived as it is as the test input signal 30 to the block 4. For the other memory blocks 5, 6 and 7, the test patterns having the bit numbers shorter than the maximum bit length are input to the test input signal 3 respectively.
It is derived as 1, 32, 33. Since the bit length of one word of the test pattern of each memory block 5, 6, 7 is known in advance, it is assumed that the number of bits of each signal 31, 32, 33 is predetermined accordingly.

FIG. 3 is a schematic diagram of test patterns used for testing individual memory blocks. Similar to the common use of the signal lines described above, the test patterns can be shared by the individual memory blocks. Therefore, the number of test patterns stored in the test pattern storage circuit 24 is the maximum word length of the built-in memory block, which is about 1 / (the number of built-in memory blocks) compared with the number of test patterns of the conventional memory circuit device. It can be estimated that

In the above embodiment, all memory circuits have different bit lengths and word lengths, but they may have the same bit length.

FIG. 4 is a block diagram of a memory circuit device according to the second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 of this embodiment is that a comparison circuit 43 is added. Yes, the comparison circuit 43 outputs the test signals from the individual memory blocks and the memory block test signal generation circuit 24.
A comparison result signal 45 is output by comparing and collating with the expected value signal 44 that is output.

In the first embodiment, the output signal at the time of testing each memory block is judged by the external LSI tester of the memory circuit device, but in this embodiment, the judgment function is carried out inside the semiconductor memory integrated circuit device. I had it. According to this embodiment, the number of required signal terminals can be greatly reduced as compared with the first embodiment.

[0028]

As described above, in the memory circuit device according to the present invention, the test pattern is prevented from increasing for testing a plurality of memory blocks having different bit lengths and word lengths. There is an effect that the restriction of the LSI tester due to the upper limit of the number of patterns is eliminated, and a semiconductor memory integrated circuit device having a short test time and high productivity can be realized.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a diagram schematically showing an operating mechanism of an input signal distribution circuit according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing a test pattern used in an example of the present invention.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional memory circuit device.

FIG. 6 is a block diagram showing another example of a conventional memory circuit device.

FIG. 7 is a diagram schematically showing a test pattern used in a conventional memory circuit device.

[Explanation of symbols]

 4 to 7 memory block 8 to 11 memory circuit 12 to 15 selector 24 test pattern storage circuit 25 input signal distribution circuit 34 memory block test signal generation circuit 43 signal comparison circuit

Claims (2)

[Claims] 1. A plurality of memory circuits having different bit lengths and word lengths, and preset test pattern data having a bit length and a word length respectively equal to the maximum bit length and the maximum word length of the memory circuits. The stored test pattern storage means and each test pattern word in the test pattern storage means are respectively converted into bit lengths corresponding to the bit lengths of the memory circuit and simultaneously distributed and supplied as test input signals to corresponding memory circuits. And a signal distribution unit for performing the same. 2. The memory circuit according to claim 1, further comprising comparing means for respectively comparing and collating an output signal pattern output from each of the memory circuits and an input test pattern to a corresponding memory circuit. apparatus.