JPS6383999A - Fail bit memory writing system - Google Patents

Abstract

PURPOSE:To reduce a necessary address area and reduce the storage capacity of a fail bit memory by designating the write address of the fail bit memory with a signal obtained by masking partial bits of the read address designating address signal of a memory device to be checked. CONSTITUTION:When the memory device to be checked is checked, data in the address designated by an address signal 14 of the memory device to be checked is read out and is compared with an expected value. If this comparison results in disaccord, a fail write signal 18 is generated because a fail bit is decided. Consequently, data '1' is written in the address of a fail bit memory 10 designated by a signal 16 obtained by masking partial bits of the address signal 14 at this time. Since plural mats of the memory device to be checked are compressed into one mat and fail bits are marked in this form, the storage capacity of the fail bit memory 10 is considerably reduced in comparison with the storage capacity of the memory device to be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an 8-input system for fail bit memory in which fail bits of a memory device under test are marked in a memory testing system.

[Prior Art] Generally, in a memory testing system, specific data is allocated to each address of a memory device under test, and then,
The data stored at each address in the test memory device is read out and compared with the expected value data (JF included data), and if they do not match, write (mark) data “1” to the corresponding address in the fail bit memory. It has become. The write address of such a fail bit memory is specified using the address signal for specifying the read address of the memory device under test as it is.

Then, by analyzing the data stored in the fail bit memory, a method for repairing the fail bit of the memory device under test is determined, and a determination is made as to whether the fail bit can be repaired or not.

[Problem to be Solved] As mentioned above, conventionally, in order to mark the fail bit of the wave test memory device in the fail memory, which has a one-to-one address correspondence with the memory device under test, It is necessary to prepare fail bit memory with a capacity equal to or larger than the storage capacity.

Therefore, as the storage capacity of memory devices increases in recent years, the cost of fail-bit memory increases, which is one of the reasons for the rise in the price of memory testing systems.

Furthermore, increasing the capacity of the fail bit memory has led to an increase in the time required to read and analyze the stored data.

[Object of the Invention] Therefore, an object of the present invention is to provide a fail bit memory writing method for solving such conventional problems.

[Means for Solving the Problems] In order to achieve this object, the present invention includes an L stage that generates a signal in which a partial bit of the read address designation phase address signal of the memory device under test is masked. Then, the signal generated by this means is given to the fail bit memory as an address signal to perform writing into the fail bit memory.

[Operation: In this way, some bits of the address number for specifying the read address of the memory device under test are masked.
Since the address of the fail bit memory is specified by the code, a plurality of addresses of the memory device to be tested are associated with one address of the fail bit memory. In other words, the fail pits of the memory to be inspected are marked in a compressed form, and the address area required for the marking can be reduced. Therefore, the storage capacity of the fail bit memory can be reduced, or fail pits in a memory device with a larger capacity than the fail bit memory can be marked.

Also, by the amount of reduction in storage capacity of fail bit memory,
The time for reading and analyzing the stored data is shortened.

Here, memory cells RT in a memory device are generally divided into a plurality of mats, and the number of divisions is 2 to the nth power (
n=L 2.3.・Since it is a fist Φ,), some bits of the address signal (two-dimensional address signal in the X direction and Y direction) are mat selection bits. Therefore, by masking the mat selection bit of such an address signal, a plurality of mats can be compressed into one mat and the fail bit can be marked in the fail bit memory.

On the other hand, in general, repair of fail pits in a memory device is not performed at one pit (), but at the corresponding address bit group (line in the X or Y direction) of multiple mats, and This is done by allocating redundant lines for relief prepared in advance to the mats.In other words, multiple mats are handled in parallel.

Therefore, as mentioned above, multiple cloaks are rolled together (
Even if you mark the fail pit in the compressed) form,
There is no particular disadvantage in the analysis that it is a relief.

[Example 1] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram for explaining one embodiment of a fail bit memory writing method according to the present invention.

In this figure, 10 is a fail bit memory,
12 is a mask gate circuit.

Reference numeral 14 denotes an address signal for designating a read address of a memory device to be tested (not shown), which is input to the mask gate circuit 12 from a testing section (not shown) of the memory device testing system. This mask gate circuit 12 outputs a signal 16 in which some bits of the input address signal 14 for mat selection are masked. This signal 16 is
It is given to the fail bit memory 10 as a write address signal.

Conventionally, a circuit corresponding to the mask gate circuit 12 is not provided, and the address (ij'"J' l 4
is manually stored in the fail bit memory 10 as it is.

Reference numeral 18 denotes a fail write signal and - which are supplied from the test section to the fail bit memory 10 in synchronization with the address signal 12 when a fail bit of the memory device to be tested is detected. This signal is the same as the conventional one.

Reference numeral 20 denotes a special data signal applied to the input data pin of the fail bit memory 10, and is generally fixed at the "1" level.

In such a configuration, when testing a memory device under test, data at an address designated by the address signal 14 of the memory device under test is read out and compared with an expected value. If a match is not found in the comparison, the fail write signal 18 is generated because the focus at that address is a fail pit. Therefore, the ``1'' data is written to the address of the fail bit memory 10 specified by the signal 16 which is obtained by masking some bits of the address signal 14 at that time.

In this way, the fail pits of the memory device under test are marked in the fail bit memory 10 as 11'' data.

Here, the address signal 16 for designating the write address is a signal obtained by masking some bits of the address signal 14 for mat designation. Therefore, as described above, multiple mats of the memory device under test are compressed into one mat, and the fail pits are marked in the fail bit memory 10, so that the storage capacity of the fail bit memory 1o is reduced to the memory capacity of the memory device under test. This can be significantly reduced compared to storage capacity. In other words, by using the fail bit memory 10 with a certain storage capacity, it is possible to record fail pits in a memory device with a considerably larger storage capacity.

When the recording of the fail pits is completed in this way, the fail bit memory 1o is read out. Address designation at this time is done by an address signal (not shown), but the access is made only to the address (designated by the address copy 16) that is the access target when the fail bit memory 10 is written.

The read data signal 22 is sent to an analysis processing section (not shown) of the memory device inspection system, where processing such as determination of a fail pit relief method (assignment of a redundant line) and determination of the number of relief operations are performed.

Here, as described above, the fail pits of the memory device under test are compressed and recorded in the fail bit memory 10 in the form of a plurality of overlapping mats determined by the mask bits of the address signal 14. therefore,
By the amount of compression, the fail bit memory is 10 times larger than before.
The data read time and analysis processing time are shortened.

In this analysis process, as described above, the fail pit relief method is determined in units of corresponding address bits R\ (lines in the X direction or Y direction) of multiple mats, so There is no inconvenience.

Incidentally, the mask gate circuit 12 in the above embodiment has r
It masks some specified bits.
The bits to be masked may be specified externally.

Furthermore, depending on how the bits to be masked are selected, the addresses specified by the masked address signal 16 may be irregular. In this case, a memory device as the fail bit memory 10 may be installed only in the address range to be marked.

[Effects of the Invention] As explained above, in the fail bit memory writing method according to the present invention, the fail bit memory is occupied by a signal in which some bits of the address signal for specifying the read address of the memory device under test are masked. It is possible to compress the fail pits of the memory device under test and record them in the fail bit memory while specifying the address of the memory device under test. It is possible to quickly test the memory device, and it is also possible to shorten the time required to read and analyze data stored in the fail bit memory.

Then, as described above, if the mat selection bit is selected as the bit to be masked in the address signal, fail bit relief etc. can be performed in the same manner as before.

As described above, according to the present invention, it is possible to reduce the storage capacitance of the fail bit memory and shorten the time required for fail bit repair analysis, etc., without causing any particular inconvenience.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram for explaining one embodiment of a fail bit memory writing method according to the present invention. DESCRIPTION OF SYMBOLS 10...Fail bit memory, 12...Mask gate circuit, 14...Address signal, 16...Address signal after masking, 18...Fail write signal.

Claims (2)

[Claims] (1) It has means for creating a signal that masks some bits of the address signal for specifying the read address of the memory device under test, and the signal created by this means is given to the fail bit memory as an address signal, and the fail bit A fail bit memory write method characterized by writing to memory. (2) The fail bit memory writing method according to claim 1, wherein some masked bits of the address signal are mat selection bits of a memory device to be tested.