JPH0561713A - Electronic circuit block testing circuit - Google Patents

Abstract

PURPOSE:To obtain an electronic circuit block testing circuit which can be composed of a comparatively small circuit for test and can monitor real operations as well without requiring a lot of test patterns concerning the test of an electronic circuit. CONSTITUTION:When an input address 6 is a prescribed address value an input address identification circuit 2 generates an input switching signal 7 at every block 1 of the electronic circuit, and an input switching circuit 3 is connected so as to selectively input either normal input data 8 or test input data 9 to the block 1. Only when the input switching signal 7 is received, the test input data 9 are inputted to the block 1, and an output address identification circuit 4 receives the input of an output address 10. When the output address 10 is a prescribed address value, an output switching signal 11 is generated and an output switching circuit 5 is connected so as to selectively output either normal output data 12 or test input data 9 only. Only when the output switching signal 11 is received, the normal output data 12 are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention inputs required test input data for testing required blocks of an electronic circuit,
The present invention relates to an electronic circuit block test circuit provided in an electronic circuit so as to extract output data.

[0002]

2. Description of the Related Art There is a so-called serial scan method as a method for testing an electronic circuit. In the serial scan method, as is well known, flip-flops (hereinafter referred to as FF) in a circuit are connected in series so as to form a scan chain.

In the test, FF can be set to a required value by inputting test data into the scan chain in bit series, and the scan chain can be read out in series to know the state.

Further, there is an address scan system, and an address decoding circuit is incorporated so that an FF can be designated by inputting an address, and the FF can be freely read / written for each specific FF designated by the address. To be able to.

However, in the serial scan method as described above, the test data must be input as a bit-serial test pattern into the chain connecting all the FFs, so that the number of types of patterns required for testing is very large. Therefore, there is a problem that the number of tests becomes large.

In the address scan system, the above-mentioned problems are small, but since the address decoding must be performed for each FF required for the test, the scale of the circuit attached for the test becomes large.

Further, in any of the methods, a test operation of setting test data in the FF and then reading the FF is necessary. The circuit under test is allowed to perform a normal operation, and the test is required during the operation. It is not possible to perform operations such as taking out and monitoring the status of various places.

An object of the present invention is to provide an electronic circuit block test circuit which can be constituted by a relatively small test circuit, does not require a large number of test patterns, and can also monitor actual operation.

[0009]

FIG. 1 is a block diagram showing the configuration of the present invention. FIG. 1A shows a configuration of an electronic circuit block test circuit, in which an input address identification circuit 2, an input switching circuit 3, and an input address identification circuit 2 are provided for each required block 1 of the electronic circuit.
An output address identification circuit 4 and an output switching circuit 5 are provided.

Input address identification circuit 2 receives input of input address 6 and generates an input switching signal 7 when input address 6 has a predetermined address value. The input switching circuit 3 is connected so as to selectively input one of the normal input data 8 and the test input data 9 to the block 1, and receives the test input data 9 from the block 1 only when receiving the input switching signal 7. To enter.

The output address identification circuit 4 outputs the output address.
In response to the input of 10, the output switching signal 11 is generated when the output address 10 has a predetermined address value. The output switching circuit 5 is connected to selectively output one of the normal output data 12 and the test input data 9 of the block 1 and outputs the normal output data 12 only when receiving the output switching signal 11. ..

When a plurality of the circuits 13a, 13b, ... Are provided, the input address 6 and the output address 10 are connected in parallel to all the circuits as shown in FIG. 1 (b). And input the test input data 9 to one of the circuits, and each of the circuits other than the circuit sequentially outputs the output of the output switching circuit 5 of the other circuit to the test input data 9. Connect in series.

[0013]

With the above-described structure of the present invention, it is possible to directly specify the required circuit blocks individually by the input address and the output address with respect to the circuit block requiring the test. It becomes possible to directly specify and input the test data, and to specify the same block or another necessary block by the output address and directly take out the output of the block.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1 (a), an input address identification circuit 2
The output address identification circuit 4 receives the input address or the output address as an input, decodes the address, and turns on the input switching signal 7 or the output switching signal 11 only at a specific address. Can be configured.

The address value of the specific address to be identified is
As is clear from the purpose of this circuit, when there are a plurality of blocks connected together, a unique value is assigned to each block. Since the values of the input address and the output address have no relation in control, they may be assigned completely independently, but the input side and the output side of the same block may have the same address.

Further, if one address, for example, "0" of the address value is reserved as a reserved address which is not always assigned to any block, only one of the input and the output is used as the test path. When switching, and the other is held in the normal state, the 0 address can be used as an address for keeping the normal state, so that control can be performed easily and less likely to cause an error.

When it is necessary to control the test operation, a test instruction signal TEST is provided as shown in the figure and is connected to the input address identification circuit 2 and the output address identification circuit 4 to control the output signal. .. That is, the specific address assigned to the circuit as described above is input, and TE
Only when ST is on, the input switching signal and the output switching signal are turned on.

FIG. 1B shows the principle of connection between a plurality of blocks. If necessary, an appropriate control circuit is added before and after the block group in the figure to reduce the number of input / output terminals. be able to.

That is, FIG. 2A shows a structure in which a terminal dedicated to an input address is unnecessary by using a terminal for normal input data for inputting an input address in the case of a test. It is provided and the switching is controlled by the TEST signal.

A similar configuration may be applied to the output address or the test input data if the test context allows. If the data width is appropriate, see Fig. 2 (b).
The input address, the output address and the test input data may all be input from the terminal of the normal input data through the gate circuit 21 as in the example shown in FIG. Good.

FIG. 3 shows an example in which at least one of the input address and the output address is set in the register 23 of the FF to reduce the number of input terminals, and FIG. 4 shows the test input data and the test output data in the shift register 24, This is an example of relaying at 25 and reducing the required number of the relevant terminals to one.

Needless to say, the respective methods shown in FIGS. 2 to 4 can be used by appropriately combining them. Further, each electronic circuit block in the above description may be one block in one integrated circuit component, a single integrated circuit component, or one assembled on an electronic circuit board. ..

In this system, since the block whose input or output should be switched is directly designated, the data flow between blocks during actual operation and the connection order of test input data between blocks may be irrelevant. For example, even when there is a branch in the connection between blocks as in the example of FIG. 5, the test input data may be connected so as to pass through all blocks in series in an appropriate order.

[0024]

As is apparent from the above description, according to the present invention, a mechanism for testing an electronic circuit can be configured with a relatively small test circuit, and a large number of test patterns are required for testing. Notwithstanding, there is a remarkable industrial effect that monitoring during actual operation becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a connection between blocks.

[Explanation of symbols]

 1 electronic circuit block 2 input address identification circuit 3 input switching circuit 4 output address identification circuit 5 output switching circuit 6 input address 7 input switching signal 8 normal input data 9 test input data 10 output address 11 output switching signal 12 normal output data 13a- 13d block

Claims (2)

[Claims] 1. For each required block (1) of an electronic circuit,
An input address identification circuit (2), an input switching circuit (3), an output address identification circuit (4), and an output switching circuit (5) are provided, and the input address identification circuit (2) is provided with an input address (6 ), The input switching signal (7) is generated when the input address has a predetermined address value, and the input switching circuit (3) outputs the normal input data (8) and the test input data (8). 9) and one of them are selectively connected to the block (1) and the test input data are input to the block only when the input switching signal (7) is received. The identification circuit (4) receives the input of the output address (10) and generates an output switching signal (11) when the output address has a predetermined address value, and the output switching circuit (5) Normal output data of the block (1)
One of the (12) and the test input data (9) is connected to selectively output, and is configured to output the normal output data only when receiving the output switching signal (11). An electronic circuit block test circuit characterized in that 2. A plurality of circuits (13a etc.) according to claim 1 are provided, and the input address (6) and the output address (10) are respectively supplied to all the circuits in parallel, and the test is performed. The input data (9) is input to one of the circuits, and each of the circuits other than the corresponding circuit outputs the output switching circuit (1
An electronic circuit block test circuit, which is sequentially connected so that the output of 1) is used as the test input data.