JPS60221842A - Fault diagnosing circuit of logical device - Google Patents

Abstract

PURPOSE:To detect the contents of a register having no scan bus, too, and to decrease the hardware of a circuit by reading the contents of a register to a register having a scan bus by utilizing a bus line, when diagnosing a fault of a logical device having a bus structure. CONSTITUTION:When a control signal on a mode switching control signal bus 240 of a fault diagnosing circuit of a logical device is in a diagnostic mode, a register 211 and 221 of integrated circuits 210, 220 hold the contents. Also, the contents of a register 231 of an integrated circuit 230 are read out of a scan output, and the contents of the register 211 are read to the register 231 through a bus line. Its contents are read out as a scan output, and subsequently, the contents of the register 221 are read out as a scan output. In such a way, the contents of all the registers 211, 221 and 231 are detected, a faulty part is retrieved, and the hardware of the circuit is decreased.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a bus refill for an information processing device.

In particular, it relates to a fault diagnosis circuit for logic circuits.

[Description of prior art]

Many logic devices, including computers, employ pass circuits, and recent large-scale integrated circuits have logic circuits or register circuits on the same chip as the driver/receiver used to drive and receive pass lines. Increasingly, this is the case.

On the other hand, the scan path method is widely used as a fault diagnosis method for logical devices. The scan path method connects many registers in the device in series to form a shift register, and can be switched between two modes: normal register function and shift register function during diagnosis. In the diagnostic mode, one bit is read every clock from the output of the serially connected shift registers, the contents of all registers are detected, and the fault location can be searched. be exposed.

Therefore, since scan paths are configured for all registers, the amount of hardware increases accordingly.

FIG. 1 is a logical block configuration diagram showing the configuration of a conventional device. In FIG. 1, reference numerals 110, 120, and 130 indicate n-bit path drivers/receivers 112 to 11n connected to the n-bit path line 100, respectively.

122 to 12n, and 132 to 13n1 and n-bit registers 111, 121, and 131, respectively, with reference numerals 161, 162, and 163.
and 164, and 165 and 166 are the scan input and scan output of registers 01 and 121.131, respectively, and 117 is the register 111.1.
21 and 131 are control signals for mode switching between operating as a normal register and as a shift register in a diagnostic mode, and reference numeral 11B is a clock signal. That is, FIG. 1 shows that all registers have a scan function.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of a logic device having a path structure, and to provide a fault diagnosis circuit for a logic device that is configured with a smaller amount of hardware than conventional circuits.

C. Summary of the Invention The present invention provides a diagnostic screen for one set of registers among the plurality of registers in a logic device including a plurality of sets of registers and a path line connected in parallel to the contents of the registers. The present invention is characterized by comprising a campus, and circuit means for reading the contents of registers other than the one set of registers into the one set of registers via the pass line when diagnosing a failure of the logic device.

[Explanation based on examples]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 2 is a block diagram showing the configuration of the apparatus of this embodiment.

First, the configuration of this embodiment device will be explained based on FIG. This embodiment device is composed of a path line 200, integrated circuits 210, 220, and 230, a mode switching control signal path 240, a clock signal path 250, and a scan path 260, where the integrated circuit 210 is ,
Register 211 and bus driver/receiver 212-21
The integrated circuit 220 is composed of a register 221 and a register 221.
The integrated circuit 230 includes a receiver 231 and bus drivers/receivers 222 to 22n.
It is composed of receivers 232 to 23n. pass line 2
00 is bus driver/receiver 112~lln, 22
2 to 22n and 232" to exchange data signals with the registers 211, 221 and 23n.
The first input/output of 31 is the bus driver/receiver 212~
The second inputs of registers 211.221 and 231 are connected to the mode switching control signal path, and the second inputs of registers 211.221 and 231 are connected to the mode switching control signal path. A third input is connected to clock signal path 250 and a fourth input of register 231 is connected to scan path 2.
60 and the second output of register 231 is connected to the other of scan path 260.

Next, the operation of this embodiment device will be explained based on FIG. 2. When the control signal on the mode switching control signal path 240 is in the diagnostic mode, the contents of the register 211 and the register 221 are held, and the contents of the register 231 are the scan output 2.
16, the contents of register 211 are then read into register 231 via pass line 200, the contents are read out as scan output 216, and then the contents of register 221 are read out via pass line 200. The data is read into the register 231, and its contents are read out as the scan output 216. In this way, the contents of all registers 211, 221, and 231 are detected, and the location of the failure is searched.

In this example device, the number of integrated circuits is three, but
The present invention can also be practiced with a number other than three.

〔Effect of the invention〕

As explained above, when diagnosing a fault in a logic device having a bus structure, the present invention reads the contents of a register into a register having a scan path using a path line, thereby also reading the contents of a register without a scan path. Since the detection is possible, the amount of hardware associated with the scan path is reduced, which has the effect of reducing costs.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of a conventional device. FIG. 2 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. 100.200...pass line, 110.120.1
30.210.220.230... integrated circuit, 111
, 121 , 131.211.221.231...
Register, 112 mi 122.132.212.222.
232...Path driver/receiver, 240...Mode switching control signal path, 250...Clock signal path. Patent applicant: NEC Corporation7. :r Agent Patent attorney Nao Ide 4 Atsushi 1 Figure

Claims (1)

[Claims] (1) In a logic device including a plurality of sets of registers and a path line connected in parallel to the contents of the registers, a scan path for diagnosis is provided for one set of registers among the plurality of sets of registers, A fault diagnostic circuit for a logic device, comprising circuit means for reading contents of registers other than the one set of registers into the one set of registers via the pass line when diagnosing a fault in the device.